Lines Matching +full:v +full:- +full:blanking
1 // SPDX-License-Identifier: GPL-2.0-only
35 * This is how it is defined by CEA-861-D - line and pixel numbers are
44 * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge).
50 * 23 blanking lines
56 * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
57 * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
61 * vtotal = mode->crtc_vtotal + 1;
62 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
63 * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
65 * vtotal = mode->crtc_vtotal;
66 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
67 * vhorizpos = mode->crtc_hsync_start;
69 * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
83 while (regs->offset != ~0) { in armada_drm_crtc_update_regs()
84 void __iomem *reg = dcrtc->base + regs->offset; in armada_drm_crtc_update_regs()
87 val = regs->mask; in armada_drm_crtc_update_regs()
90 writel_relaxed(val | regs->val, reg); in armada_drm_crtc_update_regs()
99 dumb_ctrl = dcrtc->cfg_dumb_ctrl; in armada_drm_crtc_update()
108 * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode. in armada_drm_crtc_update()
117 dcrtc->base + LCD_SPU_DUMB_CTRL); in armada_drm_crtc_update()
126 event = xchg(&crtc->state->event, NULL); in armada_drm_crtc_queue_state_event()
129 dcrtc->event = event; in armada_drm_crtc_queue_state_event()
135 struct drm_property_blob *blob = crtc->state->gamma_lut; in armada_drm_update_gamma()
136 void __iomem *base = drm_to_armada_crtc(crtc)->base; in armada_drm_update_gamma()
140 struct drm_color_lut *lut = blob->data; in armada_drm_update_gamma()
176 if (mode->vscan > 1) in armada_drm_crtc_mode_valid()
179 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) in armada_drm_crtc_mode_valid()
182 if (mode->flags & DRM_MODE_FLAG_HSKEW) in armada_drm_crtc_mode_valid()
186 if (!dcrtc->variant->has_spu_adv_reg && in armada_drm_crtc_mode_valid()
187 mode->flags & DRM_MODE_FLAG_INTERLACE) in armada_drm_crtc_mode_valid()
190 if (mode->flags & (DRM_MODE_FLAG_BCAST | DRM_MODE_FLAG_PIXMUX | in armada_drm_crtc_mode_valid()
219 ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL); in armada_drm_crtc_mode_fixup()
226 /* These are locked by dev->vbl_lock */
229 if (dcrtc->irq_ena & mask) { in armada_drm_crtc_disable_irq()
230 dcrtc->irq_ena &= ~mask; in armada_drm_crtc_disable_irq()
231 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_disable_irq()
237 if ((dcrtc->irq_ena & mask) != mask) { in armada_drm_crtc_enable_irq()
238 dcrtc->irq_ena |= mask; in armada_drm_crtc_enable_irq()
239 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_enable_irq()
240 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask) in armada_drm_crtc_enable_irq()
241 writel(0, dcrtc->base + LCD_SPU_IRQ_ISR); in armada_drm_crtc_enable_irq()
248 void __iomem *base = dcrtc->base; in armada_drm_crtc_irq()
251 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num); in armada_drm_crtc_irq()
253 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num); in armada_drm_crtc_irq()
256 drm_crtc_handle_vblank(&dcrtc->crtc); in armada_drm_crtc_irq()
258 spin_lock(&dcrtc->irq_lock); in armada_drm_crtc_irq()
259 if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) { in armada_drm_crtc_irq()
263 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH); in armada_drm_crtc_irq()
264 writel_relaxed(dcrtc->v[i].spu_v_h_total, in armada_drm_crtc_irq()
269 val |= dcrtc->v[i].spu_adv_reg; in armada_drm_crtc_irq()
273 if (stat & dcrtc->irq_ena & DUMB_FRAMEDONE) { in armada_drm_crtc_irq()
274 if (dcrtc->update_pending) { in armada_drm_crtc_irq()
275 armada_drm_crtc_update_regs(dcrtc, dcrtc->regs); in armada_drm_crtc_irq()
276 dcrtc->update_pending = false; in armada_drm_crtc_irq()
278 if (dcrtc->cursor_update) { in armada_drm_crtc_irq()
279 writel_relaxed(dcrtc->cursor_hw_pos, in armada_drm_crtc_irq()
281 writel_relaxed(dcrtc->cursor_hw_sz, in armada_drm_crtc_irq()
287 dcrtc->cursor_update = false; in armada_drm_crtc_irq()
291 spin_unlock(&dcrtc->irq_lock); in armada_drm_crtc_irq()
293 if (stat & VSYNC_IRQ && !dcrtc->update_pending) { in armada_drm_crtc_irq()
294 event = xchg(&dcrtc->event, NULL); in armada_drm_crtc_irq()
296 spin_lock(&dcrtc->crtc.dev->event_lock); in armada_drm_crtc_irq()
297 drm_crtc_send_vblank_event(&dcrtc->crtc, event); in armada_drm_crtc_irq()
298 spin_unlock(&dcrtc->crtc.dev->event_lock); in armada_drm_crtc_irq()
299 drm_crtc_vblank_put(&dcrtc->crtc); in armada_drm_crtc_irq()
307 u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR); in armada_drm_irq() local
311 * is set. Writing has some other effect to acknowledge the IRQ - in armada_drm_irq()
314 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); in armada_drm_irq()
316 trace_armada_drm_irq(&dcrtc->crtc, stat); in armada_drm_irq()
319 v = stat & dcrtc->irq_ena; in armada_drm_irq()
321 if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) { in armada_drm_irq()
331 struct drm_display_mode *adj = &crtc->state->adjusted_mode; in armada_drm_crtc_mode_set_nofb()
337 bool interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE); in armada_drm_crtc_mode_set_nofb()
340 rm = adj->crtc_hsync_start - adj->crtc_hdisplay; in armada_drm_crtc_mode_set_nofb()
341 lm = adj->crtc_htotal - adj->crtc_hsync_end; in armada_drm_crtc_mode_set_nofb()
342 bm = adj->crtc_vsync_start - adj->crtc_vdisplay; in armada_drm_crtc_mode_set_nofb()
343 tm = adj->crtc_vtotal - adj->crtc_vsync_end; in armada_drm_crtc_mode_set_nofb()
346 crtc->base.id, crtc->name, DRM_MODE_ARG(adj)); in armada_drm_crtc_mode_set_nofb()
350 dcrtc->variant->compute_clock(dcrtc, adj, &sclk); in armada_drm_crtc_mode_set_nofb()
354 spin_lock_irqsave(&dcrtc->irq_lock, flags); in armada_drm_crtc_mode_set_nofb()
356 dcrtc->interlaced = interlaced; in armada_drm_crtc_mode_set_nofb()
358 dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 | in armada_drm_crtc_mode_set_nofb()
359 adj->crtc_htotal; in armada_drm_crtc_mode_set_nofb()
360 dcrtc->v[1].spu_v_porch = tm << 16 | bm; in armada_drm_crtc_mode_set_nofb()
361 val = adj->crtc_hsync_start; in armada_drm_crtc_mode_set_nofb()
362 dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN; in armada_drm_crtc_mode_set_nofb()
366 val -= adj->crtc_htotal / 2; in armada_drm_crtc_mode_set_nofb()
367 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN; in armada_drm_crtc_mode_set_nofb()
368 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total + in armada_drm_crtc_mode_set_nofb()
370 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1; in armada_drm_crtc_mode_set_nofb()
372 dcrtc->v[0] = dcrtc->v[1]; in armada_drm_crtc_mode_set_nofb()
375 val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay; in armada_drm_crtc_mode_set_nofb()
379 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH); in armada_drm_crtc_mode_set_nofb()
380 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total, in armada_drm_crtc_mode_set_nofb()
383 if (dcrtc->variant->has_spu_adv_reg) in armada_drm_crtc_mode_set_nofb()
384 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg, in armada_drm_crtc_mode_set_nofb()
388 val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0; in armada_drm_crtc_mode_set_nofb()
396 * The non-inverted state of the sync signals is active high. in armada_drm_crtc_mode_set_nofb()
400 if (adj->flags & DRM_MODE_FLAG_NCSYNC) in armada_drm_crtc_mode_set_nofb()
402 if (adj->flags & DRM_MODE_FLAG_NHSYNC) in armada_drm_crtc_mode_set_nofb()
404 if (adj->flags & DRM_MODE_FLAG_NVSYNC) in armada_drm_crtc_mode_set_nofb()
411 spin_unlock_irqrestore(&dcrtc->irq_lock, flags); in armada_drm_crtc_mode_set_nofb()
419 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); in armada_drm_crtc_atomic_check()
421 if (crtc_state->gamma_lut && drm_color_lut_size(crtc_state->gamma_lut) != 256) in armada_drm_crtc_atomic_check()
422 return -EINVAL; in armada_drm_crtc_atomic_check()
424 if (crtc_state->color_mgmt_changed) in armada_drm_crtc_atomic_check()
425 crtc_state->planes_changed = true; in armada_drm_crtc_atomic_check()
437 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); in armada_drm_crtc_atomic_begin()
439 if (crtc_state->color_mgmt_changed) in armada_drm_crtc_atomic_begin()
442 dcrtc->regs_idx = 0; in armada_drm_crtc_atomic_begin()
443 dcrtc->regs = dcrtc->atomic_regs; in armada_drm_crtc_atomic_begin()
453 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); in armada_drm_crtc_atomic_flush()
455 armada_reg_queue_end(dcrtc->regs, dcrtc->regs_idx); in armada_drm_crtc_atomic_flush()
462 dcrtc->update_pending = true; in armada_drm_crtc_atomic_flush()
464 spin_lock_irq(&dcrtc->irq_lock); in armada_drm_crtc_atomic_flush()
466 spin_unlock_irq(&dcrtc->irq_lock); in armada_drm_crtc_atomic_flush()
468 spin_lock_irq(&dcrtc->irq_lock); in armada_drm_crtc_atomic_flush()
469 armada_drm_crtc_update_regs(dcrtc, dcrtc->regs); in armada_drm_crtc_atomic_flush()
470 spin_unlock_irq(&dcrtc->irq_lock); in armada_drm_crtc_atomic_flush()
482 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); in armada_drm_crtc_atomic_disable()
484 if (old_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) in armada_drm_crtc_atomic_disable()
490 if (!crtc->state->active) { in armada_drm_crtc_atomic_disable()
495 if (dcrtc->variant->disable) in armada_drm_crtc_atomic_disable()
496 dcrtc->variant->disable(dcrtc); in armada_drm_crtc_atomic_disable()
502 event = crtc->state->event; in armada_drm_crtc_atomic_disable()
503 crtc->state->event = NULL; in armada_drm_crtc_atomic_disable()
505 spin_lock_irq(&crtc->dev->event_lock); in armada_drm_crtc_atomic_disable()
507 spin_unlock_irq(&crtc->dev->event_lock); in armada_drm_crtc_atomic_disable()
519 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); in armada_drm_crtc_atomic_enable()
521 if (!old_state->active) { in armada_drm_crtc_atomic_enable()
524 * been disabled. Reverse the call to ->disable in in armada_drm_crtc_atomic_enable()
527 if (dcrtc->variant->enable) in armada_drm_crtc_atomic_enable()
528 dcrtc->variant->enable(dcrtc, &crtc->state->adjusted_mode); in armada_drm_crtc_atomic_enable()
533 if (crtc->state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) in armada_drm_crtc_atomic_enable()
603 uint32_t xoff, xscr, w = dcrtc->cursor_w, s; in armada_drm_crtc_cursor_update()
604 uint32_t yoff, yscr, h = dcrtc->cursor_h; in armada_drm_crtc_cursor_update()
611 if (dcrtc->cursor_x < 0) { in armada_drm_crtc_cursor_update()
612 xoff = -dcrtc->cursor_x; in armada_drm_crtc_cursor_update()
614 w -= min(xoff, w); in armada_drm_crtc_cursor_update()
615 } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) { in armada_drm_crtc_cursor_update()
617 xscr = dcrtc->cursor_x; in armada_drm_crtc_cursor_update()
618 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0); in armada_drm_crtc_cursor_update()
621 xscr = dcrtc->cursor_x; in armada_drm_crtc_cursor_update()
624 if (dcrtc->cursor_y < 0) { in armada_drm_crtc_cursor_update()
625 yoff = -dcrtc->cursor_y; in armada_drm_crtc_cursor_update()
627 h -= min(yoff, h); in armada_drm_crtc_cursor_update()
628 } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) { in armada_drm_crtc_cursor_update()
630 yscr = dcrtc->cursor_y; in armada_drm_crtc_cursor_update()
631 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0); in armada_drm_crtc_cursor_update()
634 yscr = dcrtc->cursor_y; in armada_drm_crtc_cursor_update()
638 s = dcrtc->cursor_w; in armada_drm_crtc_cursor_update()
639 if (dcrtc->interlaced) { in armada_drm_crtc_cursor_update()
645 if (!dcrtc->cursor_obj || !h || !w) { in armada_drm_crtc_cursor_update()
646 spin_lock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
647 dcrtc->cursor_update = false; in armada_drm_crtc_cursor_update()
648 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); in armada_drm_crtc_cursor_update()
649 spin_unlock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
653 spin_lock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
654 para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1); in armada_drm_crtc_cursor_update()
656 dcrtc->base + LCD_SPU_SRAM_PARA1); in armada_drm_crtc_cursor_update()
657 spin_unlock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
664 armada_drm_crtc_cursor_tran(dcrtc->base); in armada_drm_crtc_cursor_update()
668 if (dcrtc->cursor_hw_sz != (h << 16 | w)) { in armada_drm_crtc_cursor_update()
669 spin_lock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
670 dcrtc->cursor_update = false; in armada_drm_crtc_cursor_update()
671 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); in armada_drm_crtc_cursor_update()
672 spin_unlock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
676 struct armada_gem_object *obj = dcrtc->cursor_obj; in armada_drm_crtc_cursor_update()
678 /* Set the top-left corner of the cursor image */ in armada_drm_crtc_cursor_update()
679 pix = obj->addr; in armada_drm_crtc_cursor_update()
681 armada_load_cursor_argb(dcrtc->base, pix, s, w, h); in armada_drm_crtc_cursor_update()
685 spin_lock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
686 dcrtc->cursor_hw_pos = yscr << 16 | xscr; in armada_drm_crtc_cursor_update()
687 dcrtc->cursor_hw_sz = h << 16 | w; in armada_drm_crtc_cursor_update()
688 dcrtc->cursor_update = true; in armada_drm_crtc_cursor_update()
690 spin_unlock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
708 if (!dcrtc->variant->has_spu_adv_reg) in armada_drm_crtc_cursor_set()
709 return -ENXIO; in armada_drm_crtc_cursor_set()
714 return -ENOMEM; in armada_drm_crtc_cursor_set()
718 return -ENOENT; in armada_drm_crtc_cursor_set()
720 /* Must be a kernel-mapped object */ in armada_drm_crtc_cursor_set()
721 if (!obj->addr) { in armada_drm_crtc_cursor_set()
722 drm_gem_object_put(&obj->obj); in armada_drm_crtc_cursor_set()
723 return -EINVAL; in armada_drm_crtc_cursor_set()
726 if (obj->obj.size < w * h * 4) { in armada_drm_crtc_cursor_set()
728 drm_gem_object_put(&obj->obj); in armada_drm_crtc_cursor_set()
729 return -ENOMEM; in armada_drm_crtc_cursor_set()
733 if (dcrtc->cursor_obj) { in armada_drm_crtc_cursor_set()
734 dcrtc->cursor_obj->update = NULL; in armada_drm_crtc_cursor_set()
735 dcrtc->cursor_obj->update_data = NULL; in armada_drm_crtc_cursor_set()
736 drm_gem_object_put(&dcrtc->cursor_obj->obj); in armada_drm_crtc_cursor_set()
738 dcrtc->cursor_obj = obj; in armada_drm_crtc_cursor_set()
739 dcrtc->cursor_w = w; in armada_drm_crtc_cursor_set()
740 dcrtc->cursor_h = h; in armada_drm_crtc_cursor_set()
743 obj->update_data = dcrtc; in armada_drm_crtc_cursor_set()
744 obj->update = cursor_update; in armada_drm_crtc_cursor_set()
756 if (!dcrtc->variant->has_spu_adv_reg) in armada_drm_crtc_cursor_move()
757 return -EFAULT; in armada_drm_crtc_cursor_move()
759 dcrtc->cursor_x = x; in armada_drm_crtc_cursor_move()
760 dcrtc->cursor_y = y; in armada_drm_crtc_cursor_move()
769 struct armada_private *priv = drm_to_armada_dev(crtc->dev); in armada_drm_crtc_destroy()
771 if (dcrtc->cursor_obj) in armada_drm_crtc_destroy()
772 drm_gem_object_put(&dcrtc->cursor_obj->obj); in armada_drm_crtc_destroy()
774 priv->dcrtc[dcrtc->num] = NULL; in armada_drm_crtc_destroy()
775 drm_crtc_cleanup(&dcrtc->crtc); in armada_drm_crtc_destroy()
777 if (dcrtc->variant->disable) in armada_drm_crtc_destroy()
778 dcrtc->variant->disable(dcrtc); in armada_drm_crtc_destroy()
780 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_destroy()
782 of_node_put(dcrtc->crtc.port); in armada_drm_crtc_destroy()
801 spin_lock_irqsave(&dcrtc->irq_lock, flags); in armada_drm_crtc_enable_vblank()
803 spin_unlock_irqrestore(&dcrtc->irq_lock, flags); in armada_drm_crtc_enable_vblank()
812 spin_lock_irqsave(&dcrtc->irq_lock, flags); in armada_drm_crtc_disable_vblank()
814 spin_unlock_irqrestore(&dcrtc->irq_lock, flags); in armada_drm_crtc_disable_vblank()
847 dcrtc->crtc.base.id, dcrtc->crtc.name, desired_hz); in armada_crtc_select_clock()
854 if (params->settable & BIT(i)) { in armada_crtc_select_clock()
869 /* Calculate the divider - if invalid, we can't do this rate */ in armada_crtc_select_clock()
871 if (div == 0 || div > params->div_max) in armada_crtc_select_clock()
874 /* Calculate the actual rate - HDMI requires -0.6%..+0.5% */ in armada_crtc_select_clock()
878 dcrtc->crtc.base.id, dcrtc->crtc.name, in armada_crtc_select_clock()
884 if (permillage < params->permillage_min) in armada_crtc_select_clock()
888 if (permillage > params->permillage_max) in armada_crtc_select_clock()
894 return -ERANGE; in armada_crtc_select_clock()
898 dcrtc->crtc.base.id, dcrtc->crtc.name, in armada_crtc_select_clock()
901 res->desired_clk_hz = desired_clk_hz; in armada_crtc_select_clock()
902 res->clk = clk; in armada_crtc_select_clock()
903 res->div = div; in armada_crtc_select_clock()
925 return -ENOMEM; in armada_drm_crtc_create()
928 if (dev != drm->dev) in armada_drm_crtc_create()
931 dcrtc->variant = variant; in armada_drm_crtc_create()
932 dcrtc->base = base; in armada_drm_crtc_create()
933 dcrtc->num = drm->mode_config.num_crtc; in armada_drm_crtc_create()
934 dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0; in armada_drm_crtc_create()
935 dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24; in armada_drm_crtc_create()
936 spin_lock_init(&dcrtc->irq_lock); in armada_drm_crtc_create()
937 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR; in armada_drm_crtc_create()
940 writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV); in armada_drm_crtc_create()
941 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR); in armada_drm_crtc_create()
942 writel_relaxed(dcrtc->spu_iopad_ctrl, in armada_drm_crtc_create()
943 dcrtc->base + LCD_SPU_IOPAD_CONTROL); in armada_drm_crtc_create()
944 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0); in armada_drm_crtc_create()
947 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1); in armada_drm_crtc_create()
948 writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1); in armada_drm_crtc_create()
949 writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_create()
950 readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR); in armada_drm_crtc_create()
951 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); in armada_drm_crtc_create()
958 if (dcrtc->variant->init) { in armada_drm_crtc_create()
959 ret = dcrtc->variant->init(dcrtc, dev); in armada_drm_crtc_create()
965 armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0); in armada_drm_crtc_create()
967 priv->dcrtc[dcrtc->num] = dcrtc; in armada_drm_crtc_create()
969 dcrtc->crtc.port = port; in armada_drm_crtc_create()
973 ret = -ENOMEM; in armada_drm_crtc_create()
983 ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, primary, NULL, in armada_drm_crtc_create()
988 drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs); in armada_drm_crtc_create()
990 ret = drm_mode_crtc_set_gamma_size(&dcrtc->crtc, 256); in armada_drm_crtc_create()
994 drm_crtc_enable_color_mgmt(&dcrtc->crtc, 0, false, 256); in armada_drm_crtc_create()
996 return armada_overlay_plane_create(drm, 1 << dcrtc->num); in armada_drm_crtc_create()
999 primary->funcs->destroy(primary); in armada_drm_crtc_create()
1019 if (!dev->of_node) { in armada_lcd_bind()
1024 return -ENXIO; in armada_lcd_bind()
1026 variant = (const struct armada_variant *)id->driver_data; in armada_lcd_bind()
1029 struct device_node *np, *parent = dev->of_node; in armada_lcd_bind()
1031 match = of_match_device(dev->driver->of_match_table, dev); in armada_lcd_bind()
1033 return -ENXIO; in armada_lcd_bind()
1042 return -ENXIO; in armada_lcd_bind()
1045 variant = match->data; in armada_lcd_bind()
1056 armada_drm_crtc_destroy(&dcrtc->crtc); in armada_lcd_unbind()
1066 return component_add(&pdev->dev, &armada_lcd_ops); in armada_lcd_probe()
1071 component_del(&pdev->dev, &armada_lcd_ops); in armada_lcd_remove()
1077 .compatible = "marvell,dove-lcd",
1086 .name = "armada-lcd",
1089 .name = "armada-510-lcd",
1100 .name = "armada-lcd",