Lines Matching +full:mali +full:- +full:dp500

1 /* SPDX-License-Identifier: GPL-2.0-only */
6  * ARM Mali DP500/DP550/DP650 registers definition.
14  *    - DC - display core (general settings)
15  *    - DE - display engine
16  *    - SE - scaling engine
170 /* register offsets and bits specific to DP500 */
190  * The YUV2RGB coefficients on the DP500 are not in the video layer's register
194 #define MALIDP500_LV_YUV2RGB		((s16)(-0xB8))
214  * The quality of service (QoS) register on the DP500. RQOS register values
218  *    - RED_ARQOS   @ A 4-bit signal value for close to underflow conditions
219  *    - GREEN_ARQOS @ A 4-bit signal value for normal conditions
274 /* The following register offsets are common for DP500, DP550 and DP650 */
297  * The old DP500 IP mixes some DC with the DE registers, hence the need