169 	CLK_MAP(VCLK,		PPCLK_VCLK_0),
774 		*value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :  in sienna_cichlid_get_smu_metrics_data()
775 			use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :  in sienna_cichlid_get_smu_metrics_data()
776 			metrics->CurrClock[PPCLK_VCLK_0];  in sienna_cichlid_get_smu_metrics_data()
1028 				!table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete;  in sienna_cichlid_set_default_dpm_table()
1203 	case PPCLK_VCLK_0:  in sienna_cichlid_get_current_clk_freq_by_table()
2661 			pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,  in beige_goby_dump_pptable()
2662 			pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,  in beige_goby_dump_pptable()
2663 			pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,  in beige_goby_dump_pptable()
2664 			pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,  in beige_goby_dump_pptable()
2665 			pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,  in beige_goby_dump_pptable()
2666 			pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,  in beige_goby_dump_pptable()
2667 			pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,  in beige_goby_dump_pptable()
2668 			pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,  in beige_goby_dump_pptable()
2669 			pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,  in beige_goby_dump_pptable()
2670 			pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,  in beige_goby_dump_pptable()
2671 			pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);  in beige_goby_dump_pptable()
2745 	dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);  in beige_goby_dump_pptable()
3299 			pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,  in sienna_cichlid_dump_pptable()
3300 			pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,  in sienna_cichlid_dump_pptable()
3301 			pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,  in sienna_cichlid_dump_pptable()
3302 			pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,  in sienna_cichlid_dump_pptable()
3303 			pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,  in sienna_cichlid_dump_pptable()
3304 			pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,  in sienna_cichlid_dump_pptable()
3305 			pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,  in sienna_cichlid_dump_pptable()
3306 			pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,  in sienna_cichlid_dump_pptable()
3307 			pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,  in sienna_cichlid_dump_pptable()
3308 			pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,  in sienna_cichlid_dump_pptable()
3309 			pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);  in sienna_cichlid_dump_pptable()
3383 	dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);  in sienna_cichlid_dump_pptable()
4017 	gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :  in sienna_cichlid_get_gpu_metrics()
4018 		use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];  in sienna_cichlid_get_gpu_metrics()