954 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);  in vega10_setup_dpm_led_config()
1472 	data->smc_state_table.pp_table.UlvOffsetVid =  in vega10_populate_ulv_state()
1475 	data->smc_state_table.pp_table.UlvSmnclkDid =  in vega10_populate_ulv_state()
1477 	data->smc_state_table.pp_table.UlvMp1clkDid =  in vega10_populate_ulv_state()
1479 	data->smc_state_table.pp_table.UlvGfxclkBypass =  in vega10_populate_ulv_state()
1481 	data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 =  in vega10_populate_ulv_state()
1483 	data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 =  in vega10_populate_ulv_state()
1512 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);  in vega10_override_pcie_parameters()
1559 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);  in vega10_populate_smc_link_levels()
1721 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);  in vega10_populate_all_graphic_levels()
1776 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);  in vega10_populate_vddc_soc_levels()
1870 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);  in vega10_populate_all_memory_levels()
1913 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);  in vega10_populate_single_display_type()
2008 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);  in vega10_populate_smc_vce_levels()
2071 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);  in vega10_populate_smc_uvd_levels()
2142 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);  in vega10_populate_clock_stretcher_table()
2161 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);  in vega10_populate_avfs_parameters()
2396 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);  in vega10_populate_gpio_parameters()
2482 	AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);  in vega10_populate_and_upload_avfs_fuse_override()
2551 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);  in vega10_init_smc_table()
3622 		if (data->smc_state_table.gfx_boot_level !=  in vega10_upload_dpm_bootup_level()
3626 				data->smc_state_table.gfx_boot_level,  in vega10_upload_dpm_bootup_level()
3630 					data->smc_state_table.gfx_boot_level;  in vega10_upload_dpm_bootup_level()
3635 		if (data->smc_state_table.mem_boot_level !=  in vega10_upload_dpm_bootup_level()
3637 			if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1)  in vega10_upload_dpm_bootup_level()
3647 						data->smc_state_table.mem_boot_level,  in vega10_upload_dpm_bootup_level()
3651 					data->smc_state_table.mem_boot_level;  in vega10_upload_dpm_bootup_level()
3659 		if (data->smc_state_table.soc_boot_level !=  in vega10_upload_dpm_bootup_level()
3663 				data->smc_state_table.soc_boot_level,  in vega10_upload_dpm_bootup_level()
3666 					data->smc_state_table.soc_boot_level;  in vega10_upload_dpm_bootup_level()
3680 		if (data->smc_state_table.gfx_max_level !=  in vega10_upload_dpm_max_level()
3684 				data->smc_state_table.gfx_max_level,  in vega10_upload_dpm_max_level()
3687 					data->smc_state_table.gfx_max_level;  in vega10_upload_dpm_max_level()
3692 		if (data->smc_state_table.mem_max_level !=  in vega10_upload_dpm_max_level()
3696 					data->smc_state_table.mem_max_level,  in vega10_upload_dpm_max_level()
3699 					data->smc_state_table.mem_max_level;  in vega10_upload_dpm_max_level()
3707 		if (data->smc_state_table.soc_max_level !=  in vega10_upload_dpm_max_level()
3711 				data->smc_state_table.soc_max_level,  in vega10_upload_dpm_max_level()
3714 					data->smc_state_table.soc_max_level;  in vega10_upload_dpm_max_level()
3735 	data->smc_state_table.gfx_boot_level =  in vega10_generate_dpm_level_enable_mask()
3737 	data->smc_state_table.gfx_max_level =  in vega10_generate_dpm_level_enable_mask()
3739 	data->smc_state_table.mem_boot_level =  in vega10_generate_dpm_level_enable_mask()
3741 	data->smc_state_table.mem_max_level =  in vega10_generate_dpm_level_enable_mask()
3743 	data->smc_state_table.soc_boot_level =  in vega10_generate_dpm_level_enable_mask()
3745 	data->smc_state_table.soc_max_level =  in vega10_generate_dpm_level_enable_mask()
3754 	for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++)  in vega10_generate_dpm_level_enable_mask()
3758 	for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++)  in vega10_generate_dpm_level_enable_mask()
3761 	for (i = data->smc_state_table.soc_boot_level; i < data->smc_state_table.soc_max_level; i++)  in vega10_generate_dpm_level_enable_mask()
3793 		data->smc_state_table.pp_table.LowGfxclkInterruptThreshold =  in vega10_update_sclk_threshold()
3811 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);  in vega10_set_power_state_tasks()
4118 	data->smc_state_table.gfx_boot_level =  in vega10_force_dpm_highest()
4119 	data->smc_state_table.gfx_max_level =  in vega10_force_dpm_highest()
4121 	data->smc_state_table.mem_boot_level =  in vega10_force_dpm_highest()
4122 	data->smc_state_table.mem_max_level =  in vega10_force_dpm_highest()
4140 	data->smc_state_table.gfx_boot_level =  in vega10_force_dpm_lowest()
4141 	data->smc_state_table.gfx_max_level =  in vega10_force_dpm_lowest()
4143 	data->smc_state_table.mem_boot_level =  in vega10_force_dpm_lowest()
4144 	data->smc_state_table.mem_max_level =  in vega10_force_dpm_lowest()
4163 	data->smc_state_table.gfx_boot_level =  in vega10_unforce_dpm_levels()
4165 	data->smc_state_table.gfx_max_level =  in vega10_unforce_dpm_levels()
4167 	data->smc_state_table.mem_boot_level =  in vega10_unforce_dpm_levels()
4169 	data->smc_state_table.mem_max_level =  in vega10_unforce_dpm_levels()
4244 		data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;  in vega10_force_clock_level()
4245 		data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;  in vega10_force_clock_level()
4257 		data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0;  in vega10_force_clock_level()
4258 		data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0;  in vega10_force_clock_level()
4271 		data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0;  in vega10_force_clock_level()
4272 		data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0;  in vega10_force_clock_level()
4516 	Watermarks_t *table = &(data->smc_state_table.water_marks_table);  in vega10_set_watermarks_for_clocks_ranges()
4655 	PPTable_t *pptable = &(data->smc_state_table.pp_table);  in vega10_emit_clock_levels()
4801 	PPTable_t *pptable = &(data->smc_state_table.pp_table);  in vega10_print_clock_levels()
4926 	Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);  in vega10_display_configuration_changed_task()
5240 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);  in vega10_get_thermal_temperature_range()