177 static struct smu7_power_state *cast_phw_smu7_power_state(  in cast_phw_smu7_power_state()
184 	return (struct smu7_power_state *)hw_ps;  in cast_phw_smu7_power_state()
187 static const struct smu7_power_state *cast_const_phw_smu7_power_state(  in cast_const_phw_smu7_power_state()
194 	return (const struct smu7_power_state *)hw_ps;  in cast_const_phw_smu7_power_state()
3282 	return sizeof(struct smu7_power_state);  in smu7_get_power_state_size()
3319 	struct smu7_power_state *smu7_ps =  in smu7_apply_state_adjust_rules()
3489 	struct smu7_power_state  *smu7_ps;  in smu7_dpm_get_mclk()
3511 	struct smu7_power_state  *smu7_ps;  in smu7_dpm_get_sclk()
3534 	struct smu7_power_state *ps = (struct smu7_power_state *)hw_ps;  in smu7_dpm_patch_boot_state()
3595 	struct smu7_power_state  *smu7_power_state =  in smu7_get_pp_table_entry_callback_func_v1()  local
3596 			(struct smu7_power_state *)(&(power_state->hardware));  in smu7_get_pp_table_entry_callback_func_v1()
3640 	performance_level = &(smu7_power_state->performance_levels  in smu7_get_pp_table_entry_callback_func_v1()
3641 			[smu7_power_state->performance_level_count++]);  in smu7_get_pp_table_entry_callback_func_v1()
3644 …(smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHIC…  in smu7_get_pp_table_entry_callback_func_v1()
3649 			(smu7_power_state->performance_level_count <  in smu7_get_pp_table_entry_callback_func_v1()
3668 	performance_level = &(smu7_power_state->performance_levels  in smu7_get_pp_table_entry_callback_func_v1()
3669 			[smu7_power_state->performance_level_count++]);  in smu7_get_pp_table_entry_callback_func_v1()
3692 	struct smu7_power_state *ps;  in smu7_get_pp_table_entry_v1()
3701 	ps = (struct smu7_power_state *)(&state->hardware);  in smu7_get_pp_table_entry_v1()
3795 	struct smu7_power_state  *ps = cast_phw_smu7_power_state(power_state);  in smu7_get_pp_table_entry_callback_func_v0()
3837 	struct smu7_power_state *ps;  in smu7_get_pp_table_entry_v0()
3846 	ps = (struct smu7_power_state *)(&state->hardware);  in smu7_get_pp_table_entry_v0()
4081 	const struct smu7_power_state *smu7_ps =  in smu7_find_dpm_states_clocks_in_dpm_table()
4132 		const struct smu7_power_state *smu7_ps)  in smu7_get_maximum_link_speed()
4162 	const struct smu7_power_state *smu7_nps =  in smu7_request_link_speed_change_before_state_change()
4164 	const struct smu7_power_state *polaris10_cps =  in smu7_request_link_speed_change_before_state_change()
4312 		const struct smu7_power_state *smu7_ps)  in smu7_trim_dpm_states()
4343 	const struct smu7_power_state *smu7_ps =  in smu7_generate_dpm_level_enable_mask()
4407 	const struct smu7_power_state *smu7_ps =  in smu7_notify_link_speed_change_after_state_change()
4713 	const struct smu7_power_state *psa;  in smu7_check_states_equal()
4714 	const struct smu7_power_state *psb;  in smu7_check_states_equal()
5103 	struct smu7_power_state  *smu7_ps;  in smu7_set_sclk_od()
5145 	struct smu7_power_state  *smu7_ps;  in smu7_set_mclk_od()
5706 	const struct smu7_power_state *ps;  in smu7_get_performance_level()