Lines Matching defs:_ATOM_MEMORY_TIMING_FORMAT_V2
7721 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 struct
7723 …// memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
7724 USHORT usMRS; // mode register
7725 USHORT usEMRS; // extended mode register
7726 UCHAR ucCL; // CAS latency
7727 UCHAR ucWL; // WRITE Latency
7728 UCHAR uctRAS; // tRAS
7729 UCHAR uctRC; // tRC
7730 UCHAR uctRFC; // tRFC
7731 UCHAR uctRCDR; // tRCDR
7732 UCHAR uctRCDW; // tRCDW
7733 UCHAR uctRP; // tRP
7734 UCHAR uctRRD; // tRRD
7735 UCHAR uctWR; // tWR
7736 UCHAR uctWTR; // tWTR
7737 UCHAR uctPDIX; // tPDIX
7738 UCHAR uctFAW; // tFAW
7739 UCHAR uctAOND; // tAOND
7740 …ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
7742 UCHAR uctCCDL; //
7743 UCHAR uctCRCRL; //
7744 UCHAR uctCRCWL; //
7745 UCHAR uctCKE; //
7746 UCHAR uctCKRSE; //
7747 UCHAR uctCKRSX; //
7748 UCHAR uctFAW32; //
7749 UCHAR ucMR4lo; //
7750 UCHAR ucMR4hi; //
7751 UCHAR ucMR5lo; //
7752 UCHAR ucMR5hi; //
7753 UCHAR ucTerminator;
7754 UCHAR ucReserved;