Lines Matching defs:_ATOM_LCD_INFO_V13
3988 typedef struct _ATOM_LCD_INFO_V13 struct
3990 ATOM_COMMON_TABLE_HEADER sHeader;
3991 ATOM_DTD_FORMAT sLCDTiming;
3992 USHORT usExtInfoTableOffset;
3994 {
3998 ULONG ulReserved0;
3999 UCHAR ucLCD_Misc; // Reorganized in V13
4005 UCHAR ucPanelDefaultRefreshRate;
4006 UCHAR ucPanelIdentification;
4007 UCHAR ucSS_Id;
4008 USHORT usLCDVenderID;
4009 USHORT usLCDProductID;
4010 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13
4015 …lInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
4016 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13
4018 UCHAR ucPowerSequenceDIGONtoDE_in4Ms;
4019 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms;
4020 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms;
4021 UCHAR ucPowerSequenceDEtoDIGON_in4Ms;
4023 UCHAR ucOffDelay_in4Ms;
4024 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms;
4025 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms;
4026 UCHAR ucReserved1;
4028 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh
4029 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h
4030 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h
4031 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h
4033 …ORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode.
4034 UCHAR uceDPToLVDSRxId;
4035 UCHAR ucLcdReservd;
4036 ULONG ulReserved[2];