215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\  argument
216 	.enable_reg = SRI(reg1, block, reg_num),\
218 		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
220 		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
221 		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
223 	.ack_reg = SRI(reg2, block, reg_num),\
225 		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
227 		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
243 #define hpd_int_entry(reg_num)\  argument
244 	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
245 		IRQ_REG_ENTRY(HPD, reg_num,\
248 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
252 #define hpd_rx_int_entry(reg_num)\  argument
253 	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
254 		IRQ_REG_ENTRY(HPD, reg_num,\
257 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
260 #define pflip_int_entry(reg_num)\  argument
261 	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
262 		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
271 #define vupdate_no_lock_int_entry(reg_num)\  argument
272 	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
273 		IRQ_REG_ENTRY(OTG, reg_num,\
279 #define vblank_int_entry(reg_num)\  argument
280 	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
281 		IRQ_REG_ENTRY(OTG, reg_num,\
287 #define vline0_int_entry(reg_num)\  argument
288 	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
289 		IRQ_REG_ENTRY(OTG, reg_num,\
307 #define i2c_int_entry(reg_num) \  argument
308 	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
310 #define dp_sink_int_entry(reg_num) \  argument
311 	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
313 #define gpio_pad_int_entry(reg_num) \  argument
314 	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
316 #define dc_underflow_int_entry(reg_num) \  argument
317 	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()