Lines Matching refs:vlevel
266 int vlevel) in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() argument
271 …enum clock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context-… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
277 …vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_suppor… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
280 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
283 if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
285 …vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_suppor… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
287 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
288 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported) in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
549 unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel; in dcn32_set_phantom_stream_timing() local
550 …unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcCo… in dcn32_set_phantom_stream_timing()
551 unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel]; in dcn32_set_phantom_stream_timing()
577 pipes[0].clks_cfg.voltage = vlevel; in dcn32_set_phantom_stream_timing()
1093 int vlevel) in subvp_validate_static_schedulability() argument
1119 …if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vlevel][vba->maxMpcComb][vba->pipe_plane[pipe_… in subvp_validate_static_schedulability()
1135 else if (dcn32_subvp_vblank_admissable(dc, context, vlevel)) in subvp_validate_static_schedulability()
1137 …} else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_… in subvp_validate_static_schedulability()
1150 int *vlevel, in dcn32_full_validate_bw_helper() argument
1175 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); in dcn32_full_validate_bw_helper()
1177 if (*vlevel < context->bw_ctx.dml.soc.num_states) { in dcn32_full_validate_bw_helper()
1178 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); in dcn32_full_validate_bw_helper()
1179 vba->VoltageLevel = *vlevel; in dcn32_full_validate_bw_helper()
1191 (*vlevel == context->bw_ctx.dml.soc.num_states || in dcn32_full_validate_bw_helper()
1192 vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported || in dcn32_full_validate_bw_helper()
1217 if (*vlevel == context->bw_ctx.dml.soc.num_states && in dcn32_full_validate_bw_helper()
1227 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); in dcn32_full_validate_bw_helper()
1236 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); in dcn32_full_validate_bw_helper()
1241 for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) { in dcn32_full_validate_bw_helper()
1243 *vlevel = i; in dcn32_full_validate_bw_helper()
1248 if (*vlevel < context->bw_ctx.dml.soc.num_states in dcn32_full_validate_bw_helper()
1249 && subvp_validate_static_schedulability(dc, context, *vlevel)) in dcn32_full_validate_bw_helper()
1255 for (i = *vlevel; i >= 0; i--) { in dcn32_full_validate_bw_helper()
1257 *vlevel = i; in dcn32_full_validate_bw_helper()
1270 vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] = dm_dram_clock_change_unsupported; in dcn32_full_validate_bw_helper()
1273 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); in dcn32_full_validate_bw_helper()
1275 if (*vlevel < context->bw_ctx.dml.soc.num_states) { in dcn32_full_validate_bw_helper()
1276 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); in dcn32_full_validate_bw_helper()
1277 vba->VoltageLevel = *vlevel; in dcn32_full_validate_bw_helper()
1293 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); in dcn32_full_validate_bw_helper()
1294 vba->VoltageLevel = *vlevel; in dcn32_full_validate_bw_helper()
1348 int pipe_cnt, int vlevel) in dcn32_calculate_dlg_params() argument
1367 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] in dcn32_calculate_dlg_params()
1377 context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000; in dcn32_calculate_dlg_params()
1378 …if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fc… in dcn32_calculate_dlg_params()
1383 …usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.… in dcn32_calculate_dlg_params()
1481 …context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel]… in dcn32_calculate_dlg_params()
1483 …context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel… in dcn32_calculate_dlg_params()
1651 int vlevel = context->bw_ctx.dml.soc.num_states; in dcn32_internal_validate_bw() local
1676 dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt); in dcn32_internal_validate_bw()
1680 (vlevel == context->bw_ctx.dml.soc.num_states || in dcn32_internal_validate_bw()
1681 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported))) { in dcn32_internal_validate_bw()
1696 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn32_internal_validate_bw()
1700 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn32_internal_validate_bw()
1703 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn32_internal_validate_bw()
1705 vba->VoltageLevel = vlevel; in dcn32_internal_validate_bw()
1711 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn32_internal_validate_bw()
1911 int flag_vlevel = vlevel; in dcn32_internal_validate_bw()
1923 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn32_internal_validate_bw()
1924 if (vlevel == context->bw_ctx.dml.soc.num_states) { in dcn32_internal_validate_bw()
1935 vlevel = i; in dcn32_internal_validate_bw()
1945 *vlevel_out = vlevel; in dcn32_internal_validate_bw()
1962 int vlevel) in dcn32_calculate_wm_and_dlg_fpu() argument
1966 …double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vb… in dcn32_calculate_wm_and_dlg_fpu()
1969 …bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.ma… in dcn32_calculate_wm_and_dlg_fpu()
1986 …context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w… in dcn32_calculate_wm_and_dlg_fpu()
1992 context, pipes, pipe_cnt, vlevel); in dcn32_calculate_wm_and_dlg_fpu()
2004 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); in dcn32_calculate_wm_and_dlg_fpu()
2007 …context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w… in dcn32_calculate_wm_and_dlg_fpu()
2018 pstate_en && vlevel != 0)) { in dcn32_calculate_wm_and_dlg_fpu()
2028 context, pipes, pipe_cnt, vlevel); in dcn32_calculate_wm_and_dlg_fpu()
2046 if (vlevel_temp < vlevel) { in dcn32_calculate_wm_and_dlg_fpu()
2047 vlevel = vlevel_temp; in dcn32_calculate_wm_and_dlg_fpu()
2049 …dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.… in dcn32_calculate_wm_and_dlg_fpu()
2051 … context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank; in dcn32_calculate_wm_and_dlg_fpu()
2063 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); in dcn32_calculate_wm_and_dlg_fpu()
2146 pipes[0].clks_cfg.voltage = vlevel; in dcn32_calculate_wm_and_dlg_fpu()
2148 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn32_calculate_wm_and_dlg_fpu()
2161 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] == in dcn32_calculate_wm_and_dlg_fpu()
2267 dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); in dcn32_calculate_wm_and_dlg_fpu()