190 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_…  in dcn32_build_wm_range_table_fpu()
192 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_pa…  in dcn32_build_wm_range_table_fpu()
210 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;  in dcn32_build_wm_range_table_fpu()
211 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;  in dcn32_build_wm_range_table_fpu()
212 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_…  in dcn32_build_wm_range_table_fpu()
213 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;  in dcn32_build_wm_range_table_fpu()
214 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter…  in dcn32_build_wm_range_table_fpu()
215 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;  in dcn32_build_wm_range_table_fpu()
216 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;  in dcn32_build_wm_range_table_fpu()
217 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz;  in dcn32_build_wm_range_table_fpu()
218 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;  in dcn32_build_wm_range_table_fpu()
2085 	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {  in dcn32_calculate_wm_and_dlg_fpu()
2086 …ram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_l…  in dcn32_calculate_wm_and_dlg_fpu()
2087 …context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B]…  in dcn32_calculate_wm_and_dlg_fpu()
2088 ….sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter…  in dcn32_calculate_wm_and_dlg_fpu()
2089 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_in…  in dcn32_calculate_wm_and_dlg_fpu()