Lines Matching refs:bw_ctx
334 dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size); in dcn30_fpu_populate_dml_writeback_from_context()
371 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || in dcn30_fpu_update_soc_for_wm_a()
372 context->bw_ctx.dml.soc.dram_clock_change_latency_us == 0) in dcn30_fpu_update_soc_for_wm_a()
373 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_update_soc_for_wm_a()
374 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_fpu_update_soc_for_wm_a()
375 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_in… in dcn30_fpu_update_soc_for_wm_a()
385 int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; in dcn30_fpu_calculate_wm_and_dlg()
387 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
388 …bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clo… in dcn30_fpu_calculate_wm_and_dlg()
393 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in dcn30_fpu_calculate_wm_and_dlg()
401 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = in dcn30_fpu_calculate_wm_and_dlg()
404 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn30_fpu_calculate_wm_and_dlg()
413 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_calculate_wm_and_dlg()
415 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; in dcn30_fpu_calculate_wm_and_dlg()
416 dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
417 …pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_ch… in dcn30_fpu_calculate_wm_and_dlg()
421 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) in dcn30_fpu_calculate_wm_and_dlg()
422 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; in dcn30_fpu_calculate_wm_and_dlg()
426 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
435 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
437 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_calculate_wm_and_dlg()
438 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_fpu_calculate_wm_and_dlg()
439 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_in… in dcn30_fpu_calculate_wm_and_dlg()
441 …context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
442 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter… in dcn30_fpu_calculate_wm_and_dlg()
443 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->b… in dcn30_fpu_calculate_wm_and_dlg()
444 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&con… in dcn30_fpu_calculate_wm_and_dlg()
445 …context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn30_fpu_calculate_wm_and_dlg()
446 …context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->b… in dcn30_fpu_calculate_wm_and_dlg()
447 …context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&… in dcn30_fpu_calculate_wm_and_dlg()
448 …context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, p… in dcn30_fpu_calculate_wm_and_dlg()
480 unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; in dcn30_fpu_calculate_wm_and_dlg()
483 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_fpu_calculate_wm_and_dlg()
486 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] == in dcn30_fpu_calculate_wm_and_dlg()
494 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn30_fpu_calculate_wm_and_dlg()
504 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_fpu_calculate_wm_and_dlg()
507 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_fpu_calculate_wm_and_dlg()
508 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_in… in dcn30_fpu_calculate_wm_and_dlg()
511 …context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
512 …context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter… in dcn30_fpu_calculate_wm_and_dlg()
513 …context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->b… in dcn30_fpu_calculate_wm_and_dlg()
514 …context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&con… in dcn30_fpu_calculate_wm_and_dlg()
515 …context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn30_fpu_calculate_wm_and_dlg()
516 …context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->b… in dcn30_fpu_calculate_wm_and_dlg()
517 …context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&… in dcn30_fpu_calculate_wm_and_dlg()
518 …context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, p… in dcn30_fpu_calculate_wm_and_dlg()
524 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c; in dcn30_fpu_calculate_wm_and_dlg()
525 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0; in dcn30_fpu_calculate_wm_and_dlg()
534 …context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
535 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter… in dcn30_fpu_calculate_wm_and_dlg()
536 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->b… in dcn30_fpu_calculate_wm_and_dlg()
537 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&con… in dcn30_fpu_calculate_wm_and_dlg()
538 …context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn30_fpu_calculate_wm_and_dlg()
539 …context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->b… in dcn30_fpu_calculate_wm_and_dlg()
540 …context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&… in dcn30_fpu_calculate_wm_and_dlg()
541 …context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, p… in dcn30_fpu_calculate_wm_and_dlg()
544 context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod; in dcn30_fpu_calculate_wm_and_dlg()
547 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; in dcn30_fpu_calculate_wm_and_dlg()
553 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
554 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn30_fpu_calculate_wm_and_dlg()
557 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
558 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
569 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && in dcn30_fpu_calculate_wm_and_dlg()
571 context->bw_ctx.dml.vba.DRAMSpeed <= 1700 && in dcn30_fpu_calculate_wm_and_dlg()
572 context->bw_ctx.dml.vba.DRAMSpeed >= 1500) { in dcn30_fpu_calculate_wm_and_dlg()
576 context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[i].dram_speed_mts; in dcn30_fpu_calculate_wm_and_dlg()
586 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_fpu_calculate_wm_and_dlg()
589 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) in dcn30_fpu_calculate_wm_and_dlg()
672 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30); in dcn30_fpu_update_bw_bounding_box()
703 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_find_dummy_latency_index_for_fw_based_mclk_switch()
707 if (context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank == in dcn30_find_dummy_latency_index_for_fw_based_mclk_switch()