Lines Matching refs:SR_ARR
218 SR_ARR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS, id), \
219 SR_ARR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, id), \
220 SR_ARR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, id), \
221 SR_ARR(DCCG_AUDIO_DTO_SOURCE, id), SR_ARR(DCCG_AUDIO_DTO0_MODULE, id), \
222 SR_ARR(DCCG_AUDIO_DTO0_PHASE, id), SR_ARR(DCCG_AUDIO_DTO1_MODULE, id), \
223 SR_ARR(DCCG_AUDIO_DTO1_PHASE, id) \
343 SR_ARR(DIO_LINKA_CNTL, id), SR_ARR(DIO_LINKB_CNTL, id), \
344 SR_ARR(DIO_LINKC_CNTL, id), SR_ARR(DIO_LINKD_CNTL, id), \
345 SR_ARR(DIO_LINKE_CNTL, id), SR_ARR(DIO_LINKF_CNTL, id) \
357 SR_ARR(DP_STREAM_MAPPER_CONTROL0, id), \
358 SR_ARR(DP_STREAM_MAPPER_CONTROL1, id), \
359 SR_ARR(DP_STREAM_MAPPER_CONTROL2, id), \
360 SR_ARR(DP_STREAM_MAPPER_CONTROL3, id), \
593 SR_ARR(DWB_ENABLE_CLK_CTRL, id), SR_ARR(DWB_MEM_PWR_CTRL, id), \
594 SR_ARR(FC_MODE_CTRL, id), SR_ARR(FC_FLOW_CTRL, id), \
595 SR_ARR(FC_WINDOW_START, id), SR_ARR(FC_WINDOW_SIZE, id), \
596 SR_ARR(FC_SOURCE_SIZE, id), SR_ARR(DWB_UPDATE_CTRL, id), \
597 SR_ARR(DWB_CRC_CTRL, id), SR_ARR(DWB_CRC_MASK_R_G, id), \
598 SR_ARR(DWB_CRC_MASK_B_A, id), SR_ARR(DWB_CRC_VAL_R_G, id), \
599 SR_ARR(DWB_CRC_VAL_B_A, id), SR_ARR(DWB_OUT_CTRL, id), \
600 SR_ARR(DWB_MMHUBBUB_BACKPRESSURE_CNT_EN, id), \
601 SR_ARR(DWB_MMHUBBUB_BACKPRESSURE_CNT, id), \
602 SR_ARR(DWB_HOST_READ_CONTROL, id), SR_ARR(DWB_SOFT_RESET, id), \
603 SR_ARR(DWB_HDR_MULT_COEF, id), SR_ARR(DWB_GAMUT_REMAP_MODE, id), \
604 SR_ARR(DWB_GAMUT_REMAP_COEF_FORMAT, id), \
605 SR_ARR(DWB_GAMUT_REMAPA_C11_C12, id), \
606 SR_ARR(DWB_GAMUT_REMAPA_C13_C14, id), \
607 SR_ARR(DWB_GAMUT_REMAPA_C21_C22, id), \
608 SR_ARR(DWB_GAMUT_REMAPA_C23_C24, id), \
609 SR_ARR(DWB_GAMUT_REMAPA_C31_C32, id), \
610 SR_ARR(DWB_GAMUT_REMAPA_C33_C34, id), \
611 SR_ARR(DWB_GAMUT_REMAPB_C11_C12, id), \
612 SR_ARR(DWB_GAMUT_REMAPB_C13_C14, id), \
613 SR_ARR(DWB_GAMUT_REMAPB_C21_C22, id), \
614 SR_ARR(DWB_GAMUT_REMAPB_C23_C24, id), \
615 SR_ARR(DWB_GAMUT_REMAPB_C31_C32, id), \
616 SR_ARR(DWB_GAMUT_REMAPB_C33_C34, id), SR_ARR(DWB_OGAM_CONTROL, id), \
617 SR_ARR(DWB_OGAM_LUT_INDEX, id), SR_ARR(DWB_OGAM_LUT_DATA, id), \
618 SR_ARR(DWB_OGAM_LUT_CONTROL, id), \
619 SR_ARR(DWB_OGAM_RAMA_START_CNTL_B, id), \
620 SR_ARR(DWB_OGAM_RAMA_START_CNTL_G, id), \
621 SR_ARR(DWB_OGAM_RAMA_START_CNTL_R, id), \
622 SR_ARR(DWB_OGAM_RAMA_START_BASE_CNTL_B, id), \
623 SR_ARR(DWB_OGAM_RAMA_START_SLOPE_CNTL_B, id), \
624 SR_ARR(DWB_OGAM_RAMA_START_BASE_CNTL_G, id), \
625 SR_ARR(DWB_OGAM_RAMA_START_SLOPE_CNTL_G, id), \
626 SR_ARR(DWB_OGAM_RAMA_START_BASE_CNTL_R, id), \
627 SR_ARR(DWB_OGAM_RAMA_START_SLOPE_CNTL_R, id), \
628 SR_ARR(DWB_OGAM_RAMA_END_CNTL1_B, id), \
629 SR_ARR(DWB_OGAM_RAMA_END_CNTL2_B, id), \
630 SR_ARR(DWB_OGAM_RAMA_END_CNTL1_G, id), \
631 SR_ARR(DWB_OGAM_RAMA_END_CNTL2_G, id), \
632 SR_ARR(DWB_OGAM_RAMA_END_CNTL1_R, id), \
633 SR_ARR(DWB_OGAM_RAMA_END_CNTL2_R, id), \
634 SR_ARR(DWB_OGAM_RAMA_OFFSET_B, id), SR_ARR(DWB_OGAM_RAMA_OFFSET_G, id), \
635 SR_ARR(DWB_OGAM_RAMA_OFFSET_R, id), \
636 SR_ARR(DWB_OGAM_RAMA_REGION_0_1, id), \
637 SR_ARR(DWB_OGAM_RAMA_REGION_2_3, id), \
638 SR_ARR(DWB_OGAM_RAMA_REGION_4_5, id), \
639 SR_ARR(DWB_OGAM_RAMA_REGION_6_7, id), \
640 SR_ARR(DWB_OGAM_RAMA_REGION_8_9, id), \
641 SR_ARR(DWB_OGAM_RAMA_REGION_10_11, id), \
642 SR_ARR(DWB_OGAM_RAMA_REGION_12_13, id), \
643 SR_ARR(DWB_OGAM_RAMA_REGION_14_15, id), \
644 SR_ARR(DWB_OGAM_RAMA_REGION_16_17, id), \
645 SR_ARR(DWB_OGAM_RAMA_REGION_18_19, id), \
646 SR_ARR(DWB_OGAM_RAMA_REGION_20_21, id), \
647 SR_ARR(DWB_OGAM_RAMA_REGION_22_23, id), \
648 SR_ARR(DWB_OGAM_RAMA_REGION_24_25, id), \
649 SR_ARR(DWB_OGAM_RAMA_REGION_26_27, id), \
650 SR_ARR(DWB_OGAM_RAMA_REGION_28_29, id), \
651 SR_ARR(DWB_OGAM_RAMA_REGION_30_31, id), \
652 SR_ARR(DWB_OGAM_RAMA_REGION_32_33, id), \
653 SR_ARR(DWB_OGAM_RAMB_START_CNTL_B, id), \
654 SR_ARR(DWB_OGAM_RAMB_START_CNTL_G, id), \
655 SR_ARR(DWB_OGAM_RAMB_START_CNTL_R, id), \
656 SR_ARR(DWB_OGAM_RAMB_START_BASE_CNTL_B, id), \
657 SR_ARR(DWB_OGAM_RAMB_START_SLOPE_CNTL_B, id), \
658 SR_ARR(DWB_OGAM_RAMB_START_BASE_CNTL_G, id), \
659 SR_ARR(DWB_OGAM_RAMB_START_SLOPE_CNTL_G, id), \
660 SR_ARR(DWB_OGAM_RAMB_START_BASE_CNTL_R, id), \
661 SR_ARR(DWB_OGAM_RAMB_START_SLOPE_CNTL_R, id), \
662 SR_ARR(DWB_OGAM_RAMB_END_CNTL1_B, id), \
663 SR_ARR(DWB_OGAM_RAMB_END_CNTL2_B, id), \
664 SR_ARR(DWB_OGAM_RAMB_END_CNTL1_G, id), \
665 SR_ARR(DWB_OGAM_RAMB_END_CNTL2_G, id), \
666 SR_ARR(DWB_OGAM_RAMB_END_CNTL1_R, id), \
667 SR_ARR(DWB_OGAM_RAMB_END_CNTL2_R, id), \
668 SR_ARR(DWB_OGAM_RAMB_OFFSET_B, id), SR_ARR(DWB_OGAM_RAMB_OFFSET_G, id), \
669 SR_ARR(DWB_OGAM_RAMB_OFFSET_R, id), \
670 SR_ARR(DWB_OGAM_RAMB_REGION_0_1, id), \
671 SR_ARR(DWB_OGAM_RAMB_REGION_2_3, id), \
672 SR_ARR(DWB_OGAM_RAMB_REGION_4_5, id), \
673 SR_ARR(DWB_OGAM_RAMB_REGION_6_7, id), \
674 SR_ARR(DWB_OGAM_RAMB_REGION_8_9, id), \
675 SR_ARR(DWB_OGAM_RAMB_REGION_10_11, id), \
676 SR_ARR(DWB_OGAM_RAMB_REGION_12_13, id), \
677 SR_ARR(DWB_OGAM_RAMB_REGION_14_15, id), \
678 SR_ARR(DWB_OGAM_RAMB_REGION_16_17, id), \
679 SR_ARR(DWB_OGAM_RAMB_REGION_18_19, id), \
680 SR_ARR(DWB_OGAM_RAMB_REGION_20_21, id), \
681 SR_ARR(DWB_OGAM_RAMB_REGION_22_23, id), \
682 SR_ARR(DWB_OGAM_RAMB_REGION_24_25, id), \
683 SR_ARR(DWB_OGAM_RAMB_REGION_26_27, id), \
684 SR_ARR(DWB_OGAM_RAMB_REGION_28_29, id), \
685 SR_ARR(DWB_OGAM_RAMB_REGION_30_31, id), \
686 SR_ARR(DWB_OGAM_RAMB_REGION_32_33, id) \
1081 SR_ARR(GSL_SOURCE_SELECT, inst), \