Lines Matching refs:SRI_ARR
199 SRI_ARR(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
200 SRI_ARR(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
201 SRI_ARR(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
202 SRI_ARR(DC_ABM1_HG_MISC_CTRL, ABM, id), \
203 SRI_ARR(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
204 SRI_ARR(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
205 SRI_ARR(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
206 SRI_ARR(BL1_PWM_USER_LEVEL, ABM, id), \
207 SRI_ARR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
208 SRI_ARR(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
209 SRI_ARR(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
210 SRI_ARR(DC_ABM1_ACE_THRES_12, ABM, id), NBIO_SR_ARR(BIOS_SCRATCH_2, id) \
216 SRI_ARR(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZF0ENDPOINT, id), \
217 SRI_ARR(AZALIA_F0_CODEC_ENDPOINT_DATA, AZF0ENDPOINT, id), \
230 SRI_ARR(VPG_GENERIC_STATUS, VPG, id), \
231 SRI_ARR(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \
232 SRI_ARR(VPG_GENERIC_PACKET_DATA, VPG, id), \
233 SRI_ARR(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \
234 SRI_ARR(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id) \
240 SRI_ARR(AFMT_INFOFRAME_CONTROL0, AFMT, id), \
241 SRI_ARR(AFMT_VBI_PACKET_CONTROL, AFMT, id), \
242 SRI_ARR(AFMT_AUDIO_PACKET_CONTROL, AFMT, id), \
243 SRI_ARR(AFMT_AUDIO_PACKET_CONTROL2, AFMT, id), \
244 SRI_ARR(AFMT_AUDIO_SRC_CONTROL, AFMT, id), \
245 SRI_ARR(AFMT_60958_0, AFMT, id), SRI_ARR(AFMT_60958_1, AFMT, id), \
246 SRI_ARR(AFMT_60958_2, AFMT, id), SRI_ARR(AFMT_MEM_PWR, AFMT, id) \
252 SRI_ARR(APG_CONTROL, APG, id), SRI_ARR(APG_CONTROL2, APG, id), \
253 SRI_ARR(APG_MEM_PWR, APG, id), SRI_ARR(APG_DBG_GEN_CONTROL, APG, id) \
259 SRI_ARR(AFMT_CNTL, DIG, id), SRI_ARR(DIG_FE_CNTL, DIG, id), \
260 SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id), \
261 SRI_ARR(HDMI_GC, DIG, id), \
262 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
263 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
264 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
265 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
266 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \
267 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \
268 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \
269 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \
270 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \
271 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \
272 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \
273 SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id), \
274 SRI_ARR(HDMI_INFOFRAME_CONTROL1, DIG, id), \
275 SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \
276 SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id), \
277 SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id), \
278 SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \
279 SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \
280 SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id), \
281 SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id), \
282 SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \
283 SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \
284 SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \
285 SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \
286 SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \
287 SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \
288 SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \
289 SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \
290 SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \
291 SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id), \
292 SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \
293 SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id), \
294 SRI_ARR(DP_SEC_TIMESTAMP, DP, id), SRI_ARR(DP_DSC_CNTL, DP, id), \
295 SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \
296 SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
297 SRI_ARR(DP_SEC_FRAMING4, DP, id), SRI_ARR(DP_GSP11_CNTL, DP, id), \
298 SRI_ARR(DME_CONTROL, DME, id), \
299 SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \
300 SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
301 SRI_ARR(DIG_FE_CNTL, DIG, id), SRI_ARR(DIG_CLOCK_PATTERN, DIG, id), \
302 SRI_ARR(DIG_FIFO_CTRL0, DIG, id) \
309 SRI_ARR(AUX_CONTROL, DP_AUX, id), SRI_ARR(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
310 SRI_ARR(AUX_DPHY_RX_CONTROL1, DP_AUX, id) \
315 AUX_REG_LIST_RI(id), SRI_ARR(AUX_DPHY_TX_CONTROL, DP_AUX, id) \
319 #define HPD_REG_LIST_RI(id) SRI_ARR(DC_HPD_CONTROL, HPD, id)
324 SRI_ARR(DIG_BE_CNTL, DIG, id), SRI_ARR(DIG_BE_EN_CNTL, DIG, id), \
325 SRI_ARR(TMDS_CTL_BITS, DIG, id), \
326 SRI_ARR(TMDS_DCBALANCER_CONTROL, DIG, id), SRI_ARR(DP_CONFIG, DP, id), \
327 SRI_ARR(DP_DPHY_CNTL, DP, id), SRI_ARR(DP_DPHY_PRBS_CNTL, DP, id), \
328 SRI_ARR(DP_DPHY_SCRAM_CNTL, DP, id), SRI_ARR(DP_DPHY_SYM0, DP, id), \
329 SRI_ARR(DP_DPHY_SYM1, DP, id), SRI_ARR(DP_DPHY_SYM2, DP, id), \
330 SRI_ARR(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
331 SRI_ARR(DP_LINK_CNTL, DP, id), SRI_ARR(DP_LINK_FRAMING_CNTL, DP, id), \
332 SRI_ARR(DP_MSE_SAT0, DP, id), SRI_ARR(DP_MSE_SAT1, DP, id), \
333 SRI_ARR(DP_MSE_SAT2, DP, id), SRI_ARR(DP_MSE_SAT_UPDATE, DP, id), \
334 SRI_ARR(DP_SEC_CNTL, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \
335 SRI_ARR(DP_DPHY_FAST_TRAINING, DP, id), SRI_ARR(DP_SEC_CNTL1, DP, id), \
336 SRI_ARR(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
337 SRI_ARR(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id) \
342 LE_DCN3_REG_LIST_RI(id), SRI_ARR(DP_DPHY_INTERNAL_CTRL, DP, id), \
361 SRI_ARR(DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC, id), \
362 SRI_ARR(DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC, id), \
363 SRI_ARR(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC, id), \
364 SRI_ARR(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, DP_STREAM_ENC, id), \
365 SRI_ARR(DP_SYM32_ENC_CONTROL, DP_SYM32_ENC, id), \
366 SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT, DP_SYM32_ENC, id), \
367 SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id), \
368 SRI_ARR(DP_SYM32_ENC_VID_MSA0, DP_SYM32_ENC, id), \
369 SRI_ARR(DP_SYM32_ENC_VID_MSA1, DP_SYM32_ENC, id), \
370 SRI_ARR(DP_SYM32_ENC_VID_MSA2, DP_SYM32_ENC, id), \
371 SRI_ARR(DP_SYM32_ENC_VID_MSA3, DP_SYM32_ENC, id), \
372 SRI_ARR(DP_SYM32_ENC_VID_MSA4, DP_SYM32_ENC, id), \
373 SRI_ARR(DP_SYM32_ENC_VID_MSA5, DP_SYM32_ENC, id), \
374 SRI_ARR(DP_SYM32_ENC_VID_MSA6, DP_SYM32_ENC, id), \
375 SRI_ARR(DP_SYM32_ENC_VID_MSA7, DP_SYM32_ENC, id), \
376 SRI_ARR(DP_SYM32_ENC_VID_MSA8, DP_SYM32_ENC, id), \
377 SRI_ARR(DP_SYM32_ENC_VID_MSA_CONTROL, DP_SYM32_ENC, id), \
378 SRI_ARR(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id), \
379 SRI_ARR(DP_SYM32_ENC_VID_FIFO_CONTROL, DP_SYM32_ENC, id), \
380 SRI_ARR(DP_SYM32_ENC_VID_STREAM_CONTROL, DP_SYM32_ENC, id), \
381 SRI_ARR(DP_SYM32_ENC_VID_VBID_CONTROL, DP_SYM32_ENC, id), \
382 SRI_ARR(DP_SYM32_ENC_SDP_CONTROL, DP_SYM32_ENC, id), \
383 SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL0, DP_SYM32_ENC, id), \
384 SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL2, DP_SYM32_ENC, id), \
385 SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL3, DP_SYM32_ENC, id), \
386 SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL5, DP_SYM32_ENC, id), \
387 SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL11, DP_SYM32_ENC, id), \
388 SRI_ARR(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, DP_SYM32_ENC, id), \
389 SRI_ARR(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, DP_SYM32_ENC, id), \
390 SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \
391 SRI_ARR(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id) \
397 SRI_ARR(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC, id), \
398 SRI_ARR(DP_DPHY_SYM32_CONTROL, DP_DPHY_SYM32, id), \
399 SRI_ARR(DP_DPHY_SYM32_STATUS, DP_DPHY_SYM32, id), \
400 SRI_ARR(DP_DPHY_SYM32_TP_CONFIG, DP_DPHY_SYM32, id), \
401 SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED0, DP_DPHY_SYM32, id), \
402 SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED1, DP_DPHY_SYM32, id), \
403 SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED2, DP_DPHY_SYM32, id), \
404 SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED3, DP_DPHY_SYM32, id), \
405 SRI_ARR(DP_DPHY_SYM32_TP_SQ_PULSE, DP_DPHY_SYM32, id), \
406 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM0, DP_DPHY_SYM32, id), \
407 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM1, DP_DPHY_SYM32, id), \
408 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM2, DP_DPHY_SYM32, id), \
409 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM3, DP_DPHY_SYM32, id), \
410 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM4, DP_DPHY_SYM32, id), \
411 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM5, DP_DPHY_SYM32, id), \
412 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM6, DP_DPHY_SYM32, id), \
413 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM7, DP_DPHY_SYM32, id), \
414 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM8, DP_DPHY_SYM32, id), \
415 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM9, DP_DPHY_SYM32, id), \
416 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM10, DP_DPHY_SYM32, id), \
417 SRI_ARR(DP_DPHY_SYM32_SAT_VC0, DP_DPHY_SYM32, id), \
418 SRI_ARR(DP_DPHY_SYM32_SAT_VC1, DP_DPHY_SYM32, id), \
419 SRI_ARR(DP_DPHY_SYM32_SAT_VC2, DP_DPHY_SYM32, id), \
420 SRI_ARR(DP_DPHY_SYM32_SAT_VC3, DP_DPHY_SYM32, id), \
421 SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL0, DP_DPHY_SYM32, id), \
422 SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL1, DP_DPHY_SYM32, id), \
423 SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL2, DP_DPHY_SYM32, id), \
424 SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL3, DP_DPHY_SYM32, id), \
425 SRI_ARR(DP_DPHY_SYM32_SAT_UPDATE, DP_DPHY_SYM32, id) \
431 SRI_ARR(CM_DEALPHA, CM, id), SRI_ARR(CM_MEM_PWR_STATUS, CM, id), \
432 SRI_ARR(CM_BIAS_CR_R, CM, id), SRI_ARR(CM_BIAS_Y_G_CB_B, CM, id), \
433 SRI_ARR(PRE_DEGAM, CNVC_CFG, id), SRI_ARR(CM_GAMCOR_CONTROL, CM, id), \
434 SRI_ARR(CM_GAMCOR_LUT_CONTROL, CM, id), \
435 SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \
436 SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \
437 SRI_ARR(CM_GAMCOR_LUT_DATA, CM, id), \
438 SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_B, CM, id), \
439 SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_G, CM, id), \
440 SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_R, CM, id), \
441 SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id), \
442 SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id), \
443 SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id), \
444 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id), \
445 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id), \
446 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id), \
447 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id), \
448 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id), \
449 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id), \
450 SRI_ARR(CM_GAMCOR_RAMB_REGION_0_1, CM, id), \
451 SRI_ARR(CM_GAMCOR_RAMB_REGION_32_33, CM, id), \
452 SRI_ARR(CM_GAMCOR_RAMB_OFFSET_B, CM, id), \
453 SRI_ARR(CM_GAMCOR_RAMB_OFFSET_G, CM, id), \
454 SRI_ARR(CM_GAMCOR_RAMB_OFFSET_R, CM, id), \
455 SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id), \
456 SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id), \
457 SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id), \
458 SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_B, CM, id), \
459 SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_G, CM, id), \
460 SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_R, CM, id), \
461 SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id), \
462 SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id), \
463 SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id), \
464 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id), \
465 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id), \
466 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id), \
467 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id), \
468 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id), \
469 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id), \
470 SRI_ARR(CM_GAMCOR_RAMA_REGION_0_1, CM, id), \
471 SRI_ARR(CM_GAMCOR_RAMA_REGION_32_33, CM, id), \
472 SRI_ARR(CM_GAMCOR_RAMA_OFFSET_B, CM, id), \
473 SRI_ARR(CM_GAMCOR_RAMA_OFFSET_G, CM, id), \
474 SRI_ARR(CM_GAMCOR_RAMA_OFFSET_R, CM, id), \
475 SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id), \
476 SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id), \
477 SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id), \
478 SRI_ARR(CM_GAMUT_REMAP_CONTROL, CM, id), \
479 SRI_ARR(CM_GAMUT_REMAP_C11_C12, CM, id), \
480 SRI_ARR(CM_GAMUT_REMAP_C13_C14, CM, id), \
481 SRI_ARR(CM_GAMUT_REMAP_C21_C22, CM, id), \
482 SRI_ARR(CM_GAMUT_REMAP_C23_C24, CM, id), \
483 SRI_ARR(CM_GAMUT_REMAP_C31_C32, CM, id), \
484 SRI_ARR(CM_GAMUT_REMAP_C33_C34, CM, id), \
485 SRI_ARR(CM_GAMUT_REMAP_B_C11_C12, CM, id), \
486 SRI_ARR(CM_GAMUT_REMAP_B_C13_C14, CM, id), \
487 SRI_ARR(CM_GAMUT_REMAP_B_C21_C22, CM, id), \
488 SRI_ARR(CM_GAMUT_REMAP_B_C23_C24, CM, id), \
489 SRI_ARR(CM_GAMUT_REMAP_B_C31_C32, CM, id), \
490 SRI_ARR(CM_GAMUT_REMAP_B_C33_C34, CM, id), \
491 SRI_ARR(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
492 SRI_ARR(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
493 SRI_ARR(OTG_H_BLANK, DSCL, id), SRI_ARR(OTG_V_BLANK, DSCL, id), \
494 SRI_ARR(SCL_MODE, DSCL, id), SRI_ARR(LB_DATA_FORMAT, DSCL, id), \
495 SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id), \
496 SRI_ARR(DSCL_CONTROL, DSCL, id), \
497 SRI_ARR(SCL_TAP_CONTROL, DSCL, id), \
498 SRI_ARR(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
499 SRI_ARR(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
500 SRI_ARR(DSCL_2TAP_CONTROL, DSCL, id), SRI_ARR(MPC_SIZE, DSCL, id), \
501 SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
502 SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
503 SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \
504 SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \
505 SRI_ARR(SCL_HORZ_FILTER_INIT, DSCL, id), \
506 SRI_ARR(SCL_HORZ_FILTER_INIT_C, DSCL, id), \
507 SRI_ARR(SCL_VERT_FILTER_INIT, DSCL, id), \
508 SRI_ARR(SCL_VERT_FILTER_INIT_C, DSCL, id), \
509 SRI_ARR(RECOUT_START, DSCL, id), SRI_ARR(RECOUT_SIZE, DSCL, id), \
510 SRI_ARR(PRE_DEALPHA, CNVC_CFG, id), SRI_ARR(PRE_REALPHA, CNVC_CFG, id), \
511 SRI_ARR(PRE_CSC_MODE, CNVC_CFG, id), \
512 SRI_ARR(PRE_CSC_C11_C12, CNVC_CFG, id), \
513 SRI_ARR(PRE_CSC_C33_C34, CNVC_CFG, id), \
514 SRI_ARR(PRE_CSC_B_C11_C12, CNVC_CFG, id), \
515 SRI_ARR(PRE_CSC_B_C33_C34, CNVC_CFG, id), \
516 SRI_ARR(CM_POST_CSC_CONTROL, CM, id), \
517 SRI_ARR(CM_POST_CSC_C11_C12, CM, id), \
518 SRI_ARR(CM_POST_CSC_C33_C34, CM, id), \
519 SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id), \
520 SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id), \
521 SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id), \
522 SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id), \
523 SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
524 SRI_ARR(CURSOR0_CONTROL, CNVC_CUR, id), \
525 SRI_ARR(CURSOR0_COLOR0, CNVC_CUR, id), \
526 SRI_ARR(CURSOR0_COLOR1, CNVC_CUR, id), \
527 SRI_ARR(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id), \
528 SRI_ARR(DPP_CONTROL, DPP_TOP, id), SRI_ARR(CM_HDR_MULT_COEF, CM, id), \
529 SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \
530 SRI_ARR(ALPHA_2BIT_LUT, CNVC_CFG, id), \
531 SRI_ARR(FCNV_FP_BIAS_R, CNVC_CFG, id), \
532 SRI_ARR(FCNV_FP_BIAS_G, CNVC_CFG, id), \
533 SRI_ARR(FCNV_FP_BIAS_B, CNVC_CFG, id), \
534 SRI_ARR(FCNV_FP_SCALE_R, CNVC_CFG, id), \
535 SRI_ARR(FCNV_FP_SCALE_G, CNVC_CFG, id), \
536 SRI_ARR(FCNV_FP_SCALE_B, CNVC_CFG, id), \
537 SRI_ARR(COLOR_KEYER_CONTROL, CNVC_CFG, id), \
538 SRI_ARR(COLOR_KEYER_ALPHA, CNVC_CFG, id), \
539 SRI_ARR(COLOR_KEYER_RED, CNVC_CFG, id), \
540 SRI_ARR(COLOR_KEYER_GREEN, CNVC_CFG, id), \
541 SRI_ARR(COLOR_KEYER_BLUE, CNVC_CFG, id), \
542 SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \
543 SRI_ARR(OBUF_MEM_PWR_CTRL, DSCL, id), \
544 SRI_ARR(DSCL_MEM_PWR_STATUS, DSCL, id), \
545 SRI_ARR(DSCL_MEM_PWR_CTRL, DSCL, id) \
551 SRI_ARR(FMT_BIT_DEPTH_CONTROL, FMT, id), SRI_ARR(FMT_CONTROL, FMT, id), \
552 SRI_ARR(FMT_DITHER_RAND_R_SEED, FMT, id), \
553 SRI_ARR(FMT_DITHER_RAND_G_SEED, FMT, id), \
554 SRI_ARR(FMT_DITHER_RAND_B_SEED, FMT, id), \
555 SRI_ARR(FMT_CLAMP_CNTL, FMT, id), \
556 SRI_ARR(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
557 SRI_ARR(FMT_MAP420_MEMORY_CONTROL, FMT, id), \
558 SRI_ARR(OPPBUF_CONTROL, OPPBUF, id), \
559 SRI_ARR(OPPBUF_3D_PARAMETERS_0, OPPBUF, id), \
560 SRI_ARR(OPPBUF_3D_PARAMETERS_1, OPPBUF, id), \
561 SRI_ARR(OPP_PIPE_CONTROL, OPP_PIPE, id) \
568 SRI_ARR(DPG_CONTROL, DPG, id), SRI_ARR(DPG_DIMENSIONS, DPG, id), \
569 SRI_ARR(DPG_OFFSET_SEGMENT, DPG, id), SRI_ARR(DPG_COLOUR_B_CB, DPG, id), \
570 SRI_ARR(DPG_COLOUR_G_Y, DPG, id), SRI_ARR(DPG_COLOUR_R_CR, DPG, id), \
571 SRI_ARR(DPG_RAMP_CONTROL, DPG, id), SRI_ARR(DPG_STATUS, DPG, id) \
577 SRI_ARR(FMT_422_CONTROL, FMT, id) \
583 SRI_ARR(AUX_CONTROL, DP_AUX, id), SRI_ARR(AUX_ARB_CONTROL, DP_AUX, id), \
584 SRI_ARR(AUX_SW_DATA, DP_AUX, id), SRI_ARR(AUX_SW_CONTROL, DP_AUX, id), \
585 SRI_ARR(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
586 SRI_ARR(AUX_DPHY_RX_CONTROL1, DP_AUX, id), \
587 SRI_ARR(AUX_SW_STATUS, DP_AUX, id) \
749 SRI_ARR(DSC_TOP_CONTROL, DSC_TOP, id), \
750 SRI_ARR(DSC_DEBUG_CONTROL, DSC_TOP, id), \
751 SRI_ARR(DSCC_CONFIG0, DSCC, id), SRI_ARR(DSCC_CONFIG1, DSCC, id), \
752 SRI_ARR(DSCC_STATUS, DSCC, id), \
753 SRI_ARR(DSCC_INTERRUPT_CONTROL_STATUS, DSCC, id), \
754 SRI_ARR(DSCC_PPS_CONFIG0, DSCC, id), \
755 SRI_ARR(DSCC_PPS_CONFIG1, DSCC, id), \
756 SRI_ARR(DSCC_PPS_CONFIG2, DSCC, id), \
757 SRI_ARR(DSCC_PPS_CONFIG3, DSCC, id), \
758 SRI_ARR(DSCC_PPS_CONFIG4, DSCC, id), \
759 SRI_ARR(DSCC_PPS_CONFIG5, DSCC, id), \
760 SRI_ARR(DSCC_PPS_CONFIG6, DSCC, id), \
761 SRI_ARR(DSCC_PPS_CONFIG7, DSCC, id), \
762 SRI_ARR(DSCC_PPS_CONFIG8, DSCC, id), \
763 SRI_ARR(DSCC_PPS_CONFIG9, DSCC, id), \
764 SRI_ARR(DSCC_PPS_CONFIG10, DSCC, id), \
765 SRI_ARR(DSCC_PPS_CONFIG11, DSCC, id), \
766 SRI_ARR(DSCC_PPS_CONFIG12, DSCC, id), \
767 SRI_ARR(DSCC_PPS_CONFIG13, DSCC, id), \
768 SRI_ARR(DSCC_PPS_CONFIG14, DSCC, id), \
769 SRI_ARR(DSCC_PPS_CONFIG15, DSCC, id), \
770 SRI_ARR(DSCC_PPS_CONFIG16, DSCC, id), \
771 SRI_ARR(DSCC_PPS_CONFIG17, DSCC, id), \
772 SRI_ARR(DSCC_PPS_CONFIG18, DSCC, id), \
773 SRI_ARR(DSCC_PPS_CONFIG19, DSCC, id), \
774 SRI_ARR(DSCC_PPS_CONFIG20, DSCC, id), \
775 SRI_ARR(DSCC_PPS_CONFIG21, DSCC, id), \
776 SRI_ARR(DSCC_PPS_CONFIG22, DSCC, id), \
777 SRI_ARR(DSCC_MEM_POWER_CONTROL, DSCC, id), \
778 SRI_ARR(DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC, id), \
779 SRI_ARR(DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC, id), \
780 SRI_ARR(DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC, id), \
781 SRI_ARR(DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC, id), \
782 SRI_ARR(DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC, id), \
783 SRI_ARR(DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC, id), \
784 SRI_ARR(DSCC_MAX_ABS_ERROR0, DSCC, id), \
785 SRI_ARR(DSCC_MAX_ABS_ERROR1, DSCC, id), \
786 SRI_ARR(DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id), \
787 SRI_ARR(DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id), \
788 SRI_ARR(DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id), \
789 SRI_ARR(DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id), \
790 SRI_ARR(DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id), \
791 SRI_ARR(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id), \
792 SRI_ARR(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id), \
793 SRI_ARR(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id), \
794 SRI_ARR(DSCCIF_CONFIG0, DSCCIF, id), \
795 SRI_ARR(DSCCIF_CONFIG1, DSCCIF, id), \
796 SRI_ARR(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id) \
1034 SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \
1035 SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \
1036 SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \
1037 SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \
1038 SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \
1039 SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
1040 SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \
1041 SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \
1042 SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \
1043 SRI_ARR(OTG_H_TOTAL, OTG, inst), \
1044 SRI_ARR(OTG_H_BLANK_START_END, OTG, inst), \
1045 SRI_ARR(OTG_H_SYNC_A, OTG, inst), SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \
1046 SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst), \
1047 SRI_ARR(OTG_V_BLANK_START_END, OTG, inst), \
1048 SRI_ARR(OTG_V_SYNC_A, OTG, inst), SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \
1049 SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \
1050 SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \
1051 SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \
1052 SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst), \
1053 SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst), \
1054 SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst), \
1055 SRI_ARR(OTG_TRIGA_CNTL, OTG, inst), \
1056 SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst), \
1057 SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst), \
1058 SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst), \
1059 SRI_ARR(OTG_STATUS, OTG, inst), SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \
1060 SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst), \
1061 SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \
1062 SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \
1063 SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \
1064 SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \
1065 SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \
1066 SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \
1067 SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst), \
1068 SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst), \
1069 SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst), \
1070 SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst), \
1071 SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst), \
1072 SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst), \
1073 SRI_ARR(CONTROL, VTG, inst), SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \
1074 SRI_ARR(OTG_GSL_CONTROL, OTG, inst), SRI_ARR(OTG_CRC_CNTL, OTG, inst), \
1075 SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst), \
1076 SRI_ARR(OTG_CRC0_DATA_B, OTG, inst), \
1077 SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst), \
1078 SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \
1079 SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \
1080 SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \
1082 SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \
1083 SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
1084 SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \
1085 SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst), \
1086 SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst), \
1087 SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst), \
1088 SRI_ARR(OTG_DSC_START_POSITION, OTG, inst), \
1089 SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst), \
1090 SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst), \
1091 SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst), \
1092 SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \
1093 SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \
1094 SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \
1095 SRI_ARR(OTG_DRR_CONTROL, OTG, inst) \
1102 SRI_ARR(NOM_PARAMETERS_0, HUBPREQ, id), \
1103 SRI_ARR(NOM_PARAMETERS_1, HUBPREQ, id), \
1104 SRI_ARR(NOM_PARAMETERS_2, HUBPREQ, id), \
1105 SRI_ARR(NOM_PARAMETERS_3, HUBPREQ, id), \
1106 SRI_ARR(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id) \
1111 SRI_ARR(DCHUBP_CNTL, HUBP, id), SRI_ARR(HUBPREQ_DEBUG_DB, HUBP, id), \
1112 SRI_ARR(HUBPREQ_DEBUG, HUBP, id), SRI_ARR(DCSURF_ADDR_CONFIG, HUBP, id), \
1113 SRI_ARR(DCSURF_TILING_CONFIG, HUBP, id), \
1114 SRI_ARR(DCSURF_SURFACE_PITCH, HUBPREQ, id), \
1115 SRI_ARR(DCSURF_SURFACE_PITCH_C, HUBPREQ, id), \
1116 SRI_ARR(DCSURF_SURFACE_CONFIG, HUBP, id), \
1117 SRI_ARR(DCSURF_FLIP_CONTROL, HUBPREQ, id), \
1118 SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \
1119 SRI_ARR(DCSURF_PRI_VIEWPORT_START, HUBP, id), \
1120 SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \
1121 SRI_ARR(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
1122 SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
1123 SRI_ARR(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
1124 SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id), \
1125 SRI_ARR(DCSURF_SEC_VIEWPORT_START_C, HUBP, id), \
1126 SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \
1127 SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id), \
1128 SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \
1129 SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id), \
1130 SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \
1131 SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id), \
1132 SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \
1133 SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id), \
1134 SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \
1135 SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id), \
1136 SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \
1137 SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id), \
1138 SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \
1139 SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id), \
1140 SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \
1141 SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, HUBPREQ, id), \
1142 SRI_ARR(DCSURF_SURFACE_INUSE, HUBPREQ, id), \
1143 SRI_ARR(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id), \
1144 SRI_ARR(DCSURF_SURFACE_INUSE_C, HUBPREQ, id), \
1145 SRI_ARR(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id), \
1146 SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id), \
1147 SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id), \
1148 SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id), \
1149 SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id), \
1150 SRI_ARR(DCSURF_SURFACE_CONTROL, HUBPREQ, id), \
1151 SRI_ARR(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id), \
1152 SRI_ARR(HUBPRET_CONTROL, HUBPRET, id), \
1153 SRI_ARR(HUBPRET_READ_LINE_STATUS, HUBPRET, id), \
1154 SRI_ARR(DCN_EXPANSION_MODE, HUBPREQ, id), \
1155 SRI_ARR(DCHUBP_REQ_SIZE_CONFIG, HUBP, id), \
1156 SRI_ARR(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id), \
1157 SRI_ARR(BLANK_OFFSET_0, HUBPREQ, id), \
1158 SRI_ARR(BLANK_OFFSET_1, HUBPREQ, id), \
1159 SRI_ARR(DST_DIMENSIONS, HUBPREQ, id), \
1160 SRI_ARR(DST_AFTER_SCALER, HUBPREQ, id), \
1161 SRI_ARR(VBLANK_PARAMETERS_0, HUBPREQ, id), \
1162 SRI_ARR(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id), \
1163 SRI_ARR(VBLANK_PARAMETERS_1, HUBPREQ, id), \
1164 SRI_ARR(VBLANK_PARAMETERS_3, HUBPREQ, id), \
1165 SRI_ARR(NOM_PARAMETERS_4, HUBPREQ, id), \
1166 SRI_ARR(NOM_PARAMETERS_5, HUBPREQ, id), \
1167 SRI_ARR(PER_LINE_DELIVERY_PRE, HUBPREQ, id), \
1168 SRI_ARR(PER_LINE_DELIVERY, HUBPREQ, id), \
1169 SRI_ARR(VBLANK_PARAMETERS_2, HUBPREQ, id), \
1170 SRI_ARR(VBLANK_PARAMETERS_4, HUBPREQ, id), \
1171 SRI_ARR(NOM_PARAMETERS_6, HUBPREQ, id), \
1172 SRI_ARR(NOM_PARAMETERS_7, HUBPREQ, id), \
1173 SRI_ARR(DCN_TTU_QOS_WM, HUBPREQ, id), \
1174 SRI_ARR(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id), \
1175 SRI_ARR(DCN_SURF0_TTU_CNTL0, HUBPREQ, id), \
1176 SRI_ARR(DCN_SURF0_TTU_CNTL1, HUBPREQ, id), \
1177 SRI_ARR(DCN_SURF1_TTU_CNTL0, HUBPREQ, id), \
1178 SRI_ARR(DCN_SURF1_TTU_CNTL1, HUBPREQ, id), \
1179 SRI_ARR(DCN_CUR0_TTU_CNTL0, HUBPREQ, id), \
1180 SRI_ARR(DCN_CUR0_TTU_CNTL1, HUBPREQ, id), \
1181 SRI_ARR(HUBP_CLK_CNTL, HUBP, id) \
1187 SRI_ARR(PREFETCH_SETTINGS, HUBPREQ, id), \
1188 SRI_ARR(PREFETCH_SETTINGS_C, HUBPREQ, id), \
1189 SRI_ARR(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id), \
1190 SRI_ARR(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id), \
1191 SRI_ARR(CURSOR_SETTINGS, HUBPREQ, id), \
1192 SRI_ARR(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \
1193 SRI_ARR(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \
1194 SRI_ARR(CURSOR_SIZE, CURSOR0_, id), \
1195 SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \
1196 SRI_ARR(CURSOR_POSITION, CURSOR0_, id), \
1197 SRI_ARR(CURSOR_HOT_SPOT, CURSOR0_, id), \
1198 SRI_ARR(CURSOR_DST_OFFSET, CURSOR0_, id), \
1199 SRI_ARR(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \
1200 SRI_ARR(DMDATA_ADDRESS_LOW, CURSOR0_, id), \
1201 SRI_ARR(DMDATA_CNTL, CURSOR0_, id), \
1202 SRI_ARR(DMDATA_SW_CNTL, CURSOR0_, id), \
1203 SRI_ARR(DMDATA_QOS_CNTL, CURSOR0_, id), \
1204 SRI_ARR(DMDATA_SW_DATA, CURSOR0_, id), \
1205 SRI_ARR(DMDATA_STATUS, CURSOR0_, id), \
1206 SRI_ARR(FLIP_PARAMETERS_0, HUBPREQ, id), \
1207 SRI_ARR(FLIP_PARAMETERS_1, HUBPREQ, id), \
1208 SRI_ARR(FLIP_PARAMETERS_2, HUBPREQ, id), \
1209 SRI_ARR(DCN_CUR1_TTU_CNTL0, HUBPREQ, id), \
1210 SRI_ARR(DCN_CUR1_TTU_CNTL1, HUBPREQ, id), \
1211 SRI_ARR(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \
1212 SRI_ARR(VMID_SETTINGS_0, HUBPREQ, id) \
1217 HUBP_REG_LIST_DCN2_COMMON_RI(id), SRI_ARR(FLIP_PARAMETERS_3, HUBPREQ, id), \
1218 SRI_ARR(FLIP_PARAMETERS_4, HUBPREQ, id), \
1219 SRI_ARR(FLIP_PARAMETERS_5, HUBPREQ, id), \
1220 SRI_ARR(FLIP_PARAMETERS_6, HUBPREQ, id), \
1221 SRI_ARR(VBLANK_PARAMETERS_5, HUBPREQ, id), \
1222 SRI_ARR(VBLANK_PARAMETERS_6, HUBPREQ, id) \
1227 HUBP_REG_LIST_DCN21_RI(id), SRI_ARR(DCN_DMDATA_VM_CNTL, HUBPREQ, id) \
1232 HUBP_REG_LIST_DCN30_RI(id), SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id), \
1233 SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id), \
1234 SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id) \
1308 SRI_ARR(CNTL, DCN_VM_CONTEXT, id), \
1309 SRI_ARR(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id), \
1310 SRI_ARR(PAGE_TABLE_BASE_ADDR_LO32, DCN_VM_CONTEXT, id), \
1311 SRI_ARR(PAGE_TABLE_START_ADDR_HI32, DCN_VM_CONTEXT, id), \
1312 SRI_ARR(PAGE_TABLE_START_ADDR_LO32, DCN_VM_CONTEXT, id), \
1313 SRI_ARR(PAGE_TABLE_END_ADDR_HI32, DCN_VM_CONTEXT, id), \
1314 SRI_ARR(PAGE_TABLE_END_ADDR_LO32, DCN_VM_CONTEXT, id) \