Lines Matching refs:SRI2_ARR
693 SRI2_ARR(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst), \
694 SRI2_ARR(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst), \
695 SRI2_ARR(MCIF_WB_BUF_PITCH, MCIF_WB, inst), \
696 SRI2_ARR(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst), \
697 SRI2_ARR(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst), \
698 SRI2_ARR(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst), \
699 SRI2_ARR(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst), \
700 SRI2_ARR(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst), \
701 SRI2_ARR(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst), \
702 SRI2_ARR(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst), \
703 SRI2_ARR(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst), \
704 SRI2_ARR(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst), \
705 SRI2_ARR(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst), \
706 SRI2_ARR(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB, inst), \
707 SRI2_ARR(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB, inst), \
708 SRI2_ARR(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst), \
709 SRI2_ARR(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst), \
710 SRI2_ARR(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst), \
711 SRI2_ARR(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst), \
712 SRI2_ARR(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst), \
713 SRI2_ARR(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst), \
714 SRI2_ARR(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst), \
715 SRI2_ARR(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst), \
716 SRI2_ARR(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst), \
717 SRI2_ARR(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MMHUBBUB, inst), \
718 SRI2_ARR(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst), \
719 SRI2_ARR(MCIF_WB_WATERMARK, MMHUBBUB, inst), \
720 SRI2_ARR(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst), \
721 SRI2_ARR(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst), \
722 SRI2_ARR(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst), \
723 SRI2_ARR(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst), \
724 SRI2_ARR(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst), \
725 SRI2_ARR(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst), \
726 SRI2_ARR(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst), \
727 SRI2_ARR(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst), \
728 SRI2_ARR(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst), \
729 SRI2_ARR(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst), \
730 SRI2_ARR(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst), \
731 SRI2_ARR(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst), \
732 SRI2_ARR(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst), \
733 SRI2_ARR(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst), \
734 SRI2_ARR(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst), \
735 SRI2_ARR(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst), \
736 SRI2_ARR(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst), \
737 SRI2_ARR(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst), \
738 SRI2_ARR(MMHUBBUB_MEM_PWR_CNTL, MMHUBBUB, inst), \
739 SRI2_ARR(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB, inst), \
740 SRI2_ARR(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB, inst), \
741 SRI2_ARR(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB, inst), \
742 SRI2_ARR(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB, inst) \