Lines Matching refs:DIG_FIFO_CTRL0
353 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7); in enc32_stream_encoder_dp_unblank()
355 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1); in enc32_stream_encoder_dp_unblank()
357 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000); in enc32_stream_encoder_dp_unblank()
359 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0); in enc32_stream_encoder_dp_unblank()
361 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000); in enc32_stream_encoder_dp_unblank()
363 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1); in enc32_stream_encoder_dp_unblank()
425 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container == 2 ? 0x1 : 0x0); in enc32_set_dig_input_mode()
434 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val); in enc32_reset_fifo()
438 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000); in enc32_reset_fifo()
447 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7); in enc32_enable_fifo()
452 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1); in enc32_enable_fifo()