Lines Matching defs:id
153 #define SRI(reg_name, block, id)\ argument
157 #define SRI2(reg_name, block, id)\ argument
161 #define SRIR(var_name, reg_name, block, id)\ argument
165 #define SRII(reg_name, block, id)\ argument
169 #define SRII_MPC_RMU(reg_name, block, id)\ argument
173 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
177 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
180 #define DCCG_SRII(reg_name, block, id)\ argument
184 #define VUPDATE_SRII(reg_name, block, id)\ argument
225 #define abm_regs(id)\ argument
245 #define audio_regs(id)\ argument
273 #define vpg_regs(id)\ argument
299 #define afmt_regs(id)\ argument
322 #define apg_regs(id)\ argument
343 #define stream_enc_regs(id)\ argument
365 #define aux_regs(id)\ argument
378 #define hpd_regs(id)\ argument
391 #define link_regs(id, phyid)\ argument
426 #define hpo_dp_stream_encoder_reg_list(id)\ argument
447 #define hpo_dp_link_encoder_reg_list(id)\ argument
471 #define dpp_regs(id)\ argument
491 #define opp_regs(id)\ argument
511 #define aux_engine_regs(id)\ argument
527 #define dwbc_regs_dcn3(id)\ argument
544 #define mcif_wb_regs_dcn3(id)\ argument
561 #define dsc_regsDCN20(id)\ argument
604 #define optc_regs(id)\ argument
622 #define hubp_regs(id)\ argument
667 #define SRII2(reg_name_pre, reg_name_post, id)\ argument
776 #define vmid_regs(id)\ argument
961 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } argument
1582 enum clock_source_id id, in dcn31_clock_source_create()