Lines Matching defs:id
165 #define SRI(reg_name, block, id)\ argument
169 #define SRI2(reg_name, block, id)\ argument
173 #define SRIR(var_name, reg_name, block, id)\ argument
177 #define SRII(reg_name, block, id)\ argument
181 #define SRII_MPC_RMU(reg_name, block, id)\ argument
185 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
189 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
192 #define DCCG_SRII(reg_name, block, id)\ argument
196 #define VUPDATE_SRII(reg_name, block, id)\ argument
237 #define abm_regs(id)\ argument
257 #define audio_regs(id)\ argument
285 #define vpg_regs(id)\ argument
311 #define afmt_regs(id)\ argument
333 #define apg_regs(id)\ argument
353 #define stream_enc_regs(id)\ argument
375 #define aux_regs(id)\ argument
388 #define hpd_regs(id)\ argument
401 #define link_regs(id, phyid)\ argument
434 #define hpo_dp_stream_encoder_reg_list(id)\ argument
455 #define hpo_dp_link_encoder_reg_list(id)\ argument
478 #define dpp_regs(id)\ argument
498 #define opp_regs(id)\ argument
518 #define aux_engine_regs(id)\ argument
534 #define dwbc_regs_dcn3(id)\ argument
551 #define mcif_wb_regs_dcn3(id)\ argument
568 #define dsc_regsDCN20(id)\ argument
607 #define optc_regs(id)\ argument
625 #define hubp_regs(id)\ argument
670 #define SRII2(reg_name_pre, reg_name_post, id)\ argument
779 #define vmid_regs(id)\ argument
965 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } argument
1584 enum clock_source_id id, in dcn31_clock_source_create()