147 #define SRI(reg_name, block, id)\  argument
151 #define SRI2(reg_name, block, id)\  argument
155 #define SRIR(var_name, reg_name, block, id)\  argument
159 #define SRII(reg_name, block, id)\  argument
163 #define SRII_MPC_RMU(reg_name, block, id)\  argument
167 #define SRII_DWB(reg_name, temp_name, block, id)\  argument
171 #define SF_DWB2(reg_name, block, id, field_name, post_fix)	\  argument
174 #define DCCG_SRII(reg_name, block, id)\  argument
178 #define VUPDATE_SRII(reg_name, block, id)\  argument
242 #define abm_regs(id)\  argument
262 #define audio_regs(id)\  argument
290 #define vpg_regs(id)\  argument
316 #define afmt_regs(id)\  argument
338 #define apg_regs(id)\  argument
358 #define stream_enc_regs(id)\  argument
380 #define aux_regs(id)\  argument
393 #define hpd_regs(id)\  argument
406 #define link_regs(id, phyid)\  argument
438 #define hpo_dp_stream_encoder_reg_list(id)\  argument
459 #define hpo_dp_link_encoder_reg_list(id)\  argument
480 #define dpp_regs(id)\  argument
500 #define opp_regs(id)\  argument
520 #define aux_engine_regs(id)\  argument
536 #define dwbc_regs_dcn3(id)\  argument
553 #define mcif_wb_regs_dcn3(id)\  argument
570 #define dsc_regsDCN314(id)\  argument
614 #define optc_regs(id)\  argument
632 #define hubp_regs(id)\  argument
677 #define SRII2(reg_name_pre, reg_name_post, id)\  argument
791 #define vmid_regs(id)\  argument
1017 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }  argument
1659 		enum clock_source_id id,  in dcn31_clock_source_create()
1816 		enum clock_source_id id,  in dcn30_clock_source_create()