131 #define SRI(reg_name, block, id)\  argument
135 #define SRI2(reg_name, block, id)\  argument
139 #define SRIR(var_name, reg_name, block, id)\  argument
143 #define SRII(reg_name, block, id)\  argument
147 #define SRII_MPC_RMU(reg_name, block, id)\  argument
151 #define SRII_DWB(reg_name, temp_name, block, id)\  argument
155 #define SF_DWB2(reg_name, block, id, field_name, post_fix)	\  argument
158 #define DCCG_SRII(reg_name, block, id)\  argument
162 #define VUPDATE_SRII(reg_name, block, id)\  argument
234 #define abm_regs(id)\  argument
254 #define audio_regs(id)\  argument
282 #define vpg_regs(id)\  argument
308 #define afmt_regs(id)\  argument
330 #define apg_regs(id)\  argument
350 #define stream_enc_regs(id)\  argument
373 #define aux_regs(id)\  argument
386 #define hpd_regs(id)\  argument
399 #define link_regs(id, phyid)\  argument
432 #define hpo_dp_stream_encoder_reg_list(id)\  argument
452 #define hpo_dp_link_encoder_reg_list(id)\  argument
475 #define dpp_regs(id)\  argument
495 #define opp_regs(id)\  argument
515 #define aux_engine_regs(id)\  argument
531 #define dwbc_regs_dcn3(id)\  argument
548 #define mcif_wb_regs_dcn3(id)\  argument
565 #define dsc_regsDCN20(id)\  argument
608 #define optc_regs(id)\  argument
626 #define hubp_regs(id)\  argument
671 #define SRII2(reg_name_pre, reg_name_post, id)\  argument
780 #define vmid_regs(id)\  argument
967 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }  argument
1587 		enum clock_source_id id,  in dcn31_clock_source_create()
1843 		enum clock_source_id id,  in dcn30_clock_source_create()