1639 	int pipe_cnt, i, pipe_idx, vlevel;  in dcn30_internal_validate_bw()  local
1667 		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);  in dcn30_internal_validate_bw()
1669 		if (vlevel < context->bw_ctx.dml.soc.num_states)  in dcn30_internal_validate_bw()
1670 			vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);  in dcn30_internal_validate_bw()
1673 	    (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||  in dcn30_internal_validate_bw()
1674 			vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported)) {  in dcn30_internal_validate_bw()
1685 		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);  in dcn30_internal_validate_bw()
1686 		if (vlevel < context->bw_ctx.dml.soc.num_states) {  in dcn30_internal_validate_bw()
1689 			vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);  in dcn30_internal_validate_bw()
1695 	if (vlevel == context->bw_ctx.dml.soc.num_states)  in dcn30_internal_validate_bw()
1868 	context->bw_ctx.dml.vba.VoltageLevel = vlevel;  in dcn30_internal_validate_bw()
1869 	*vlevel_out = vlevel;  in dcn30_internal_validate_bw()
2026 		int vlevel)  in dcn30_calculate_wm_and_dlg()  argument
2029 	dcn30_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);  in dcn30_calculate_wm_and_dlg()
2041 	int vlevel = 0;  in dcn30_validate_bandwidth()  local
2049 	out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true);  in dcn30_validate_bandwidth()
2067 		dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);  in dcn30_validate_bandwidth()