Lines Matching refs:vlevel

1833 		int vlevel,  in dcn20_validate_apply_pipe_split_flags()  argument
1896 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1897 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 && in dcn20_validate_apply_pipe_split_flags()
1898 v->ModeSupport[vlevel][0]) in dcn20_validate_apply_pipe_split_flags()
1901 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
1902 vlevel = vlevel_split; in dcn20_validate_apply_pipe_split_flags()
1920 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4) in dcn20_validate_apply_pipe_split_flags()
1922 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2) in dcn20_validate_apply_pipe_split_flags()
1936 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1; in dcn20_validate_apply_pipe_split_flags()
1940 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1; in dcn20_validate_apply_pipe_split_flags()
1948 v->ODMCombineEnablePerState[vlevel][pipe_plane]; in dcn20_validate_apply_pipe_split_flags()
2007 if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1) { in dcn20_validate_apply_pipe_split_flags()
2009 dcn20_fpu_adjust_dppclk(v, vlevel, max_mpc_comb, pipe_idx, false); in dcn20_validate_apply_pipe_split_flags()
2015 return vlevel; in dcn20_validate_apply_pipe_split_flags()
2029 int pipe_cnt, i, pipe_idx, vlevel; in dcn20_fast_validate_bw() local
2048 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn20_fast_validate_bw()
2050 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2053 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL); in dcn20_fast_validate_bw()
2097 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn20_fast_validate_bw()
2128 *vlevel_out = vlevel; in dcn20_fast_validate_bw()