797 static void dce60_resource_destruct(struct dce110_resource_pool *pool)  in dce60_resource_destruct()  argument
801 	for (i = 0; i < pool->base.pipe_count; i++) {  in dce60_resource_destruct()
802 		if (pool->base.opps[i] != NULL)  in dce60_resource_destruct()
803 			dce110_opp_destroy(&pool->base.opps[i]);  in dce60_resource_destruct()
805 		if (pool->base.transforms[i] != NULL)  in dce60_resource_destruct()
806 			dce60_transform_destroy(&pool->base.transforms[i]);  in dce60_resource_destruct()
808 		if (pool->base.ipps[i] != NULL)  in dce60_resource_destruct()
809 			dce_ipp_destroy(&pool->base.ipps[i]);  in dce60_resource_destruct()
811 		if (pool->base.mis[i] != NULL) {  in dce60_resource_destruct()
812 			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));  in dce60_resource_destruct()
813 			pool->base.mis[i] = NULL;  in dce60_resource_destruct()
816 		if (pool->base.timing_generators[i] != NULL)	{  in dce60_resource_destruct()
817 			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));  in dce60_resource_destruct()
818 			pool->base.timing_generators[i] = NULL;  in dce60_resource_destruct()
822 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {  in dce60_resource_destruct()
823 		if (pool->base.engines[i] != NULL)  in dce60_resource_destruct()
824 			dce110_engine_destroy(&pool->base.engines[i]);  in dce60_resource_destruct()
825 		if (pool->base.hw_i2cs[i] != NULL) {  in dce60_resource_destruct()
826 			kfree(pool->base.hw_i2cs[i]);  in dce60_resource_destruct()
827 			pool->base.hw_i2cs[i] = NULL;  in dce60_resource_destruct()
829 		if (pool->base.sw_i2cs[i] != NULL) {  in dce60_resource_destruct()
830 			kfree(pool->base.sw_i2cs[i]);  in dce60_resource_destruct()
831 			pool->base.sw_i2cs[i] = NULL;  in dce60_resource_destruct()
835 	for (i = 0; i < pool->base.stream_enc_count; i++) {  in dce60_resource_destruct()
836 		if (pool->base.stream_enc[i] != NULL)  in dce60_resource_destruct()
837 			kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));  in dce60_resource_destruct()
840 	for (i = 0; i < pool->base.clk_src_count; i++) {  in dce60_resource_destruct()
841 		if (pool->base.clock_sources[i] != NULL) {  in dce60_resource_destruct()
842 			dce60_clock_source_destroy(&pool->base.clock_sources[i]);  in dce60_resource_destruct()
846 	if (pool->base.abm != NULL)  in dce60_resource_destruct()
847 			dce_abm_destroy(&pool->base.abm);  in dce60_resource_destruct()
849 	if (pool->base.dmcu != NULL)  in dce60_resource_destruct()
850 			dce_dmcu_destroy(&pool->base.dmcu);  in dce60_resource_destruct()
852 	if (pool->base.dp_clock_source != NULL)  in dce60_resource_destruct()
853 		dce60_clock_source_destroy(&pool->base.dp_clock_source);  in dce60_resource_destruct()
855 	for (i = 0; i < pool->base.audio_count; i++)	{  in dce60_resource_destruct()
856 		if (pool->base.audios[i] != NULL) {  in dce60_resource_destruct()
857 			dce_aud_destroy(&pool->base.audios[i]);  in dce60_resource_destruct()
861 	if (pool->base.irqs != NULL) {  in dce60_resource_destruct()
862 		dal_irq_service_destroy(&pool->base.irqs);  in dce60_resource_destruct()
921 static void dce60_destroy_resource_pool(struct resource_pool **pool)  in dce60_destroy_resource_pool()  argument
923 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);  in dce60_destroy_resource_pool()
927 	*pool = NULL;  in dce60_destroy_resource_pool()
944 	struct dce110_resource_pool *pool)  in dce60_construct()  argument
952 	pool->base.res_cap = &res_cap;  in dce60_construct()
953 	pool->base.funcs = &dce60_res_pool_funcs;  in dce60_construct()
959 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;  in dce60_construct()
960 	pool->base.pipe_count = res_cap.num_timing_generator;  in dce60_construct()
961 	pool->base.timing_generator_count = res_cap.num_timing_generator;  in dce60_construct()
975 		pool->base.dp_clock_source =  in dce60_construct()
978 		pool->base.clock_sources[0] =  in dce60_construct()
980 		pool->base.clock_sources[1] =  in dce60_construct()
982 		pool->base.clk_src_count = 2;  in dce60_construct()
985 		pool->base.dp_clock_source =  in dce60_construct()
988 		pool->base.clock_sources[0] =  in dce60_construct()
990 		pool->base.clk_src_count = 1;  in dce60_construct()
993 	if (pool->base.dp_clock_source == NULL) {  in dce60_construct()
999 	for (i = 0; i < pool->base.clk_src_count; i++) {  in dce60_construct()
1000 		if (pool->base.clock_sources[i] == NULL) {  in dce60_construct()
1007 	pool->base.dmcu = dce_dmcu_create(ctx,  in dce60_construct()
1011 	if (pool->base.dmcu == NULL) {  in dce60_construct()
1017 	pool->base.abm = dce_abm_create(ctx,  in dce60_construct()
1021 	if (pool->base.abm == NULL) {  in dce60_construct()
1030 		pool->base.irqs = dal_irq_service_dce60_create(&init_data);  in dce60_construct()
1031 		if (!pool->base.irqs)  in dce60_construct()
1035 	for (i = 0; i < pool->base.pipe_count; i++) {  in dce60_construct()
1036 		pool->base.timing_generators[i] = dce60_timing_generator_create(  in dce60_construct()
1038 		if (pool->base.timing_generators[i] == NULL) {  in dce60_construct()
1044 		pool->base.mis[i] = dce60_mem_input_create(ctx, i);  in dce60_construct()
1045 		if (pool->base.mis[i] == NULL) {  in dce60_construct()
1051 		pool->base.ipps[i] = dce60_ipp_create(ctx, i);  in dce60_construct()
1052 		if (pool->base.ipps[i] == NULL) {  in dce60_construct()
1058 		pool->base.transforms[i] = dce60_transform_create(ctx, i);  in dce60_construct()
1059 		if (pool->base.transforms[i] == NULL) {  in dce60_construct()
1065 		pool->base.opps[i] = dce60_opp_create(ctx, i);  in dce60_construct()
1066 		if (pool->base.opps[i] == NULL) {  in dce60_construct()
1073 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {  in dce60_construct()
1074 		pool->base.engines[i] = dce60_aux_engine_create(ctx, i);  in dce60_construct()
1075 		if (pool->base.engines[i] == NULL) {  in dce60_construct()
1081 		pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);  in dce60_construct()
1082 		if (pool->base.hw_i2cs[i] == NULL) {  in dce60_construct()
1088 		pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);  in dce60_construct()
1089 		if (pool->base.sw_i2cs[i] == NULL) {  in dce60_construct()
1097 	dc->caps.max_planes =  pool->base.pipe_count;  in dce60_construct()
1104 	if (!resource_construct(num_virtual_links, dc, &pool->base,  in dce60_construct()
1114 	dce60_resource_destruct(pool);  in dce60_construct()
1122 	struct dce110_resource_pool *pool =  in dce60_create_resource_pool()  local
1125 	if (!pool)  in dce60_create_resource_pool()
1128 	if (dce60_construct(num_virtual_links, dc, pool))  in dce60_create_resource_pool()
1129 		return &pool->base;  in dce60_create_resource_pool()
1131 	kfree(pool);  in dce60_create_resource_pool()
1139 	struct dce110_resource_pool *pool)  in dce61_construct()  argument
1147 	pool->base.res_cap = &res_cap_61;  in dce61_construct()
1148 	pool->base.funcs = &dce60_res_pool_funcs;  in dce61_construct()
1154 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;  in dce61_construct()
1155 	pool->base.pipe_count = res_cap_61.num_timing_generator;  in dce61_construct()
1156 	pool->base.timing_generator_count = res_cap_61.num_timing_generator;  in dce61_construct()
1169 		pool->base.dp_clock_source =  in dce61_construct()
1172 		pool->base.clock_sources[0] =  in dce61_construct()
1174 		pool->base.clock_sources[1] =  in dce61_construct()
1176 		pool->base.clock_sources[2] =  in dce61_construct()
1178 		pool->base.clk_src_count = 3;  in dce61_construct()
1181 		pool->base.dp_clock_source =  in dce61_construct()
1184 		pool->base.clock_sources[0] =  in dce61_construct()
1186 		pool->base.clock_sources[1] =  in dce61_construct()
1188 		pool->base.clk_src_count = 2;  in dce61_construct()
1191 	if (pool->base.dp_clock_source == NULL) {  in dce61_construct()
1197 	for (i = 0; i < pool->base.clk_src_count; i++) {  in dce61_construct()
1198 		if (pool->base.clock_sources[i] == NULL) {  in dce61_construct()
1205 	pool->base.dmcu = dce_dmcu_create(ctx,  in dce61_construct()
1209 	if (pool->base.dmcu == NULL) {  in dce61_construct()
1215 	pool->base.abm = dce_abm_create(ctx,  in dce61_construct()
1219 	if (pool->base.abm == NULL) {  in dce61_construct()
1228 		pool->base.irqs = dal_irq_service_dce60_create(&init_data);  in dce61_construct()
1229 		if (!pool->base.irqs)  in dce61_construct()
1233 	for (i = 0; i < pool->base.pipe_count; i++) {  in dce61_construct()
1234 		pool->base.timing_generators[i] = dce60_timing_generator_create(  in dce61_construct()
1236 		if (pool->base.timing_generators[i] == NULL) {  in dce61_construct()
1242 		pool->base.mis[i] = dce60_mem_input_create(ctx, i);  in dce61_construct()
1243 		if (pool->base.mis[i] == NULL) {  in dce61_construct()
1249 		pool->base.ipps[i] = dce60_ipp_create(ctx, i);  in dce61_construct()
1250 		if (pool->base.ipps[i] == NULL) {  in dce61_construct()
1256 		pool->base.transforms[i] = dce60_transform_create(ctx, i);  in dce61_construct()
1257 		if (pool->base.transforms[i] == NULL) {  in dce61_construct()
1263 		pool->base.opps[i] = dce60_opp_create(ctx, i);  in dce61_construct()
1264 		if (pool->base.opps[i] == NULL) {  in dce61_construct()
1271 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {  in dce61_construct()
1272 		pool->base.engines[i] = dce60_aux_engine_create(ctx, i);  in dce61_construct()
1273 		if (pool->base.engines[i] == NULL) {  in dce61_construct()
1279 		pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);  in dce61_construct()
1280 		if (pool->base.hw_i2cs[i] == NULL) {  in dce61_construct()
1286 		pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);  in dce61_construct()
1287 		if (pool->base.sw_i2cs[i] == NULL) {  in dce61_construct()
1295 	dc->caps.max_planes =  pool->base.pipe_count;  in dce61_construct()
1302 	if (!resource_construct(num_virtual_links, dc, &pool->base,  in dce61_construct()
1312 	dce60_resource_destruct(pool);  in dce61_construct()
1320 	struct dce110_resource_pool *pool =  in dce61_create_resource_pool()  local
1323 	if (!pool)  in dce61_create_resource_pool()
1326 	if (dce61_construct(num_virtual_links, dc, pool))  in dce61_create_resource_pool()
1327 		return &pool->base;  in dce61_create_resource_pool()
1329 	kfree(pool);  in dce61_create_resource_pool()
1337 	struct dce110_resource_pool *pool)  in dce64_construct()  argument
1345 	pool->base.res_cap = &res_cap_64;  in dce64_construct()
1346 	pool->base.funcs = &dce60_res_pool_funcs;  in dce64_construct()
1352 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;  in dce64_construct()
1353 	pool->base.pipe_count = res_cap_64.num_timing_generator;  in dce64_construct()
1354 	pool->base.timing_generator_count = res_cap_64.num_timing_generator;  in dce64_construct()
1367 		pool->base.dp_clock_source =  in dce64_construct()
1370 		pool->base.clock_sources[0] =  in dce64_construct()
1372 		pool->base.clock_sources[1] =  in dce64_construct()
1374 		pool->base.clk_src_count = 2;  in dce64_construct()
1377 		pool->base.dp_clock_source =  in dce64_construct()
1380 		pool->base.clock_sources[0] =  in dce64_construct()
1382 		pool->base.clk_src_count = 1;  in dce64_construct()
1385 	if (pool->base.dp_clock_source == NULL) {  in dce64_construct()
1391 	for (i = 0; i < pool->base.clk_src_count; i++) {  in dce64_construct()
1392 		if (pool->base.clock_sources[i] == NULL) {  in dce64_construct()
1399 	pool->base.dmcu = dce_dmcu_create(ctx,  in dce64_construct()
1403 	if (pool->base.dmcu == NULL) {  in dce64_construct()
1409 	pool->base.abm = dce_abm_create(ctx,  in dce64_construct()
1413 	if (pool->base.abm == NULL) {  in dce64_construct()
1422 		pool->base.irqs = dal_irq_service_dce60_create(&init_data);  in dce64_construct()
1423 		if (!pool->base.irqs)  in dce64_construct()
1427 	for (i = 0; i < pool->base.pipe_count; i++) {  in dce64_construct()
1428 		pool->base.timing_generators[i] = dce60_timing_generator_create(  in dce64_construct()
1430 		if (pool->base.timing_generators[i] == NULL) {  in dce64_construct()
1436 		pool->base.mis[i] = dce60_mem_input_create(ctx, i);  in dce64_construct()
1437 		if (pool->base.mis[i] == NULL) {  in dce64_construct()
1443 		pool->base.ipps[i] = dce60_ipp_create(ctx, i);  in dce64_construct()
1444 		if (pool->base.ipps[i] == NULL) {  in dce64_construct()
1450 		pool->base.transforms[i] = dce60_transform_create(ctx, i);  in dce64_construct()
1451 		if (pool->base.transforms[i] == NULL) {  in dce64_construct()
1457 		pool->base.opps[i] = dce60_opp_create(ctx, i);  in dce64_construct()
1458 		if (pool->base.opps[i] == NULL) {  in dce64_construct()
1465 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {  in dce64_construct()
1466 		pool->base.engines[i] = dce60_aux_engine_create(ctx, i);  in dce64_construct()
1467 		if (pool->base.engines[i] == NULL) {  in dce64_construct()
1473 		pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);  in dce64_construct()
1474 		if (pool->base.hw_i2cs[i] == NULL) {  in dce64_construct()
1480 		pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);  in dce64_construct()
1481 		if (pool->base.sw_i2cs[i] == NULL) {  in dce64_construct()
1489 	dc->caps.max_planes =  pool->base.pipe_count;  in dce64_construct()
1496 	if (!resource_construct(num_virtual_links, dc, &pool->base,  in dce64_construct()
1506 	dce60_resource_destruct(pool);  in dce64_construct()
1514 	struct dce110_resource_pool *pool =  in dce64_create_resource_pool()  local
1517 	if (!pool)  in dce64_create_resource_pool()
1520 	if (dce64_construct(num_virtual_links, dc, pool))  in dce64_create_resource_pool()
1521 		return &pool->base;  in dce64_create_resource_pool()
1523 	kfree(pool);  in dce64_create_resource_pool()