Lines Matching refs:dm_write_reg_soc15

261 	dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_GSL_WINDOW, tg110->offsets.crtc, 0);  in dce120_timing_generator_setup_global_swap_lock()
424 	dm_write_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset, value);  in dce120_timing_generator_disable_vga()
518 	dm_write_reg_soc15(  in dce120_timing_generator_set_overscan_color_black()
528 	dm_write_reg_soc15(  in dce120_timing_generator_set_overscan_color_black()
653 	dm_write_reg_soc15(tg->ctx,  in dce120_timing_generator_enable_advanced_request()
675 	dm_write_reg_soc15(  in dce120_tg_program_blank_color()
742 		dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_BLANK_CONTROL,  in dce120_tg_set_blank()
903 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS, tg110->offsets.crtc, 0);  in dce120_timing_generator_set_test_pattern()
942 			dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);  in dce120_timing_generator_set_test_pattern()
955 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);  in dce120_timing_generator_set_test_pattern()
1029 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, 0);  in dce120_timing_generator_set_test_pattern()
1032 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc, 0);  in dce120_timing_generator_set_test_pattern()
1044 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc,  value);  in dce120_timing_generator_set_test_pattern()
1045 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);  in dce120_timing_generator_set_test_pattern()
1046 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS, tg110->offsets.crtc, value);  in dce120_timing_generator_set_test_pattern()
1103 	dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC_CNTL,  in dce120_configure_crc()