Lines Matching refs:clk_src
41 (clk_src->regs->reg)
44 clk_src->base.ctx
50 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
59 struct dce110_clk_src *clk_src, in get_ss_data_entry() argument
72 ss_parm = clk_src->dvi_ss_params; in get_ss_data_entry()
73 entrys_num = clk_src->dvi_ss_params_cnt; in get_ss_data_entry()
77 ss_parm = clk_src->hdmi_ss_params; in get_ss_data_entry()
78 entrys_num = clk_src->hdmi_ss_params_cnt; in get_ss_data_entry()
82 ss_parm = clk_src->lvds_ss_params; in get_ss_data_entry()
83 entrys_num = clk_src->lvds_ss_params_cnt; in get_ss_data_entry()
90 ss_parm = clk_src->dp_ss_params; in get_ss_data_entry()
91 entrys_num = clk_src->dp_ss_params_cnt; in get_ss_data_entry()
393 struct dce110_clk_src *clk_src, in pll_adjust_pix_clk() argument
443 bp_result = clk_src->bios->funcs->adjust_pixel_clock( in pll_adjust_pix_clk()
444 clk_src->bios, &bp_adjust_pixel_clock_params); in pll_adjust_pix_clk()
472 struct dce110_clk_src *clk_src, in dce110_get_pix_clk_dividers_helper() argument
493 clk_src, in dce110_get_pix_clk_dividers_helper()
502 if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) { in dce110_get_pix_clk_dividers_helper()
521 &clk_src->calc_pll_hdmi, in dce110_get_pix_clk_dividers_helper()
527 &clk_src->calc_pll, in dce110_get_pix_clk_dividers_helper()
534 struct dce110_clk_src *clk_src, in dce112_get_pix_clk_dividers_helper() argument
569 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs); in dce110_get_pix_clk_dividers() local
584 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10; in dce110_get_pix_clk_dividers()
585 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10; in dce110_get_pix_clk_dividers()
591 pll_calc_error = dce110_get_pix_clk_dividers_helper(clk_src, in dce110_get_pix_clk_dividers()
602 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs); in dce112_get_pix_clk_dividers() local
616 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10; in dce112_get_pix_clk_dividers()
617 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10; in dce112_get_pix_clk_dividers()
623 dce112_get_pix_clk_dividers_helper(clk_src, in dce112_get_pix_clk_dividers()
629 static bool disable_spread_spectrum(struct dce110_clk_src *clk_src) in disable_spread_spectrum() argument
634 bp_ss_params.pll_id = clk_src->base.id; in disable_spread_spectrum()
637 result = clk_src->bios->funcs->enable_spread_spectrum_on_ppll( in disable_spread_spectrum()
638 clk_src->bios, in disable_spread_spectrum()
711 struct dce110_clk_src *clk_src, in enable_spread_spectrum() argument
719 clk_src, in enable_spread_spectrum()
736 bp_params.pll_id = clk_src->base.id; in enable_spread_spectrum()
744 clk_src->bios->funcs-> in enable_spread_spectrum()
746 clk_src->bios, in enable_spread_spectrum()
757 struct dce110_clk_src *clk_src, in dce110_program_pixel_clk_resync() argument
795 struct dce110_clk_src *clk_src, in dce112_program_pixel_clk_resync() argument
830 if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE) in dce112_program_pixel_clk_resync()
846 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); in dce110_program_pix_clk() local
856 disable_spread_spectrum(clk_src); in dce110_program_pix_clk()
888 if (clk_src->bios->funcs->set_pixel_clock( in dce110_program_pix_clk()
889 clk_src->bios, &bp_pc_params) != BP_RESULT_OK) in dce110_program_pix_clk()
900 if (!enable_spread_spectrum(clk_src, in dce110_program_pix_clk()
906 dce110_program_pixel_clk_resync(clk_src, in dce110_program_pix_clk()
920 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); in dce112_program_pix_clk() local
930 disable_spread_spectrum(clk_src); in dce112_program_pix_clk()
948 if (clk_src->bios->funcs->set_pixel_clock( in dce112_program_pix_clk()
949 clk_src->bios, &bp_pc_params) != BP_RESULT_OK) in dce112_program_pix_clk()
953 dce112_program_pixel_clk_resync(clk_src, in dce112_program_pix_clk()
967 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); in dcn31_program_pix_clk() local
986 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) in dcn31_program_pix_clk()
1000 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) in dcn31_program_pix_clk()
1042 if (clk_src->bios->funcs->set_pixel_clock( in dcn31_program_pix_clk()
1043 clk_src->bios, &bp_pc_params) != BP_RESULT_OK) in dcn31_program_pix_clk()
1047 dce112_program_pixel_clk_resync(clk_src, in dcn31_program_pix_clk()
1057 struct clock_source *clk_src) in dce110_clock_source_power_down() argument
1059 struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src); in dce110_clock_source_power_down()
1063 if (clk_src->dp_clk_src) in dce110_clock_source_power_down()
1068 bp_pixel_clock_params.pll_id = clk_src->id; in dce110_clock_source_power_down()
1084 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); in get_pixel_clk_frequency_100hz() local
1173 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); in dcn20_program_pix_clk() local
1196 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); in dcn20_override_dp_pix_clk() local
1219 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); in dcn3_program_pix_clk() local
1237 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) in dcn3_program_pix_clk()
1324 struct dce110_clk_src *clk_src, in get_ss_info_from_atombios() argument
1350 *ss_entries_num = clk_src->bios->funcs->get_ss_entry_number( in get_ss_info_from_atombios()
1351 clk_src->bios, in get_ss_info_from_atombios()
1374 bp_result = clk_src->bios->funcs->get_spread_spectrum_info( in get_ss_info_from_atombios()
1375 clk_src->bios, in get_ss_info_from_atombios()
1445 struct dce110_clk_src *clk_src) in ss_info_from_atombios_create() argument
1448 clk_src, in ss_info_from_atombios_create()
1450 &clk_src->dp_ss_params, in ss_info_from_atombios_create()
1451 &clk_src->dp_ss_params_cnt); in ss_info_from_atombios_create()
1453 clk_src, in ss_info_from_atombios_create()
1455 &clk_src->hdmi_ss_params, in ss_info_from_atombios_create()
1456 &clk_src->hdmi_ss_params_cnt); in ss_info_from_atombios_create()
1458 clk_src, in ss_info_from_atombios_create()
1460 &clk_src->dvi_ss_params, in ss_info_from_atombios_create()
1461 &clk_src->dvi_ss_params_cnt); in ss_info_from_atombios_create()
1463 clk_src, in ss_info_from_atombios_create()
1465 &clk_src->lvds_ss_params, in ss_info_from_atombios_create()
1466 &clk_src->lvds_ss_params_cnt); in ss_info_from_atombios_create()
1547 struct dce110_clk_src *clk_src, in dce110_clk_src_construct() argument
1558 clk_src->base.ctx = ctx; in dce110_clk_src_construct()
1559 clk_src->bios = bios; in dce110_clk_src_construct()
1560 clk_src->base.id = id; in dce110_clk_src_construct()
1561 clk_src->base.funcs = &dce110_clk_src_funcs; in dce110_clk_src_construct()
1563 clk_src->regs = regs; in dce110_clk_src_construct()
1564 clk_src->cs_shift = cs_shift; in dce110_clk_src_construct()
1565 clk_src->cs_mask = cs_mask; in dce110_clk_src_construct()
1567 if (!clk_src->bios->fw_info_valid) { in dce110_clk_src_construct()
1572 clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp; in dce110_clk_src_construct()
1578 clk_src->cs_mask->PLL_POST_DIV_PIXCLK; in dce110_clk_src_construct()
1580 calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; in dce110_clk_src_construct()
1597 clk_src->cs_mask->PLL_POST_DIV_PIXCLK; in dce110_clk_src_construct()
1599 calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; in dce110_clk_src_construct()
1612 clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency; in dce110_clk_src_construct()
1614 if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL) in dce110_clk_src_construct()
1618 ss_info_from_atombios_create(clk_src); in dce110_clk_src_construct()
1621 &clk_src->calc_pll, in dce110_clk_src_construct()
1629 min_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz/2; in dce110_clk_src_construct()
1631 max_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz; in dce110_clk_src_construct()
1635 &clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) { in dce110_clk_src_construct()
1647 struct dce110_clk_src *clk_src, in dce112_clk_src_construct() argument
1655 clk_src->base.ctx = ctx; in dce112_clk_src_construct()
1656 clk_src->bios = bios; in dce112_clk_src_construct()
1657 clk_src->base.id = id; in dce112_clk_src_construct()
1658 clk_src->base.funcs = &dce112_clk_src_funcs; in dce112_clk_src_construct()
1660 clk_src->regs = regs; in dce112_clk_src_construct()
1661 clk_src->cs_shift = cs_shift; in dce112_clk_src_construct()
1662 clk_src->cs_mask = cs_mask; in dce112_clk_src_construct()
1664 if (!clk_src->bios->fw_info_valid) { in dce112_clk_src_construct()
1669 clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp; in dce112_clk_src_construct()
1675 struct dce110_clk_src *clk_src, in dcn20_clk_src_construct() argument
1683 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); in dcn20_clk_src_construct()
1685 clk_src->base.funcs = &dcn20_clk_src_funcs; in dcn20_clk_src_construct()
1691 struct dce110_clk_src *clk_src, in dcn3_clk_src_construct() argument
1699 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); in dcn3_clk_src_construct()
1701 clk_src->base.funcs = &dcn3_clk_src_funcs; in dcn3_clk_src_construct()
1707 struct dce110_clk_src *clk_src, in dcn31_clk_src_construct() argument
1715 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); in dcn31_clk_src_construct()
1717 clk_src->base.funcs = &dcn31_clk_src_funcs; in dcn31_clk_src_construct()
1723 struct dce110_clk_src *clk_src, in dcn301_clk_src_construct() argument
1731 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); in dcn301_clk_src_construct()
1733 clk_src->base.funcs = &dcn3_clk_src_funcs; in dcn301_clk_src_construct()