105 		struct dc_state *context, bool safe_to_lower)  in dcn20_update_clocks_update_dpp_dto()  argument
117 		dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;  in dcn20_update_clocks_update_dpp_dto()
127 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct dc_state *context)  in dcn20_update_clocks_update_dentist()  argument
153 			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];  in dcn20_update_clocks_update_dentist()
184 			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];  in dcn20_update_clocks_update_dentist()
217 			struct dc_state *context,  in dcn2_update_clocks()  argument
221 	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;  in dcn2_update_clocks()
246 	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);  in dcn2_update_clocks()
281 	total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);  in dcn2_update_clocks()
324 			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);  in dcn2_update_clocks()
325 			dcn20_update_clocks_update_dentist(clk_mgr, context);  in dcn2_update_clocks()
329 				dcn20_update_clocks_update_dentist(clk_mgr, context);  in dcn2_update_clocks()
331 			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);  in dcn2_update_clocks()
344 		struct dc_state *context,  in dcn2_update_clocks_fpga()  argument
349 	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;  in dcn2_update_clocks_fpga()
450 		struct dc_state *context,  in dcn2_get_clock()  argument
456 		clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;  in dcn2_get_clock()
459 		clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;  in dcn2_get_clock()
462 		clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;  in dcn2_get_clock()
465 		clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;  in dcn2_get_clock()