57 	struct amdgpu_ih_regs *ih_regs;  in vega20_ih_init_register_offset()  local
60 		ih_regs = &adev->irq.ih.ih_regs;  in vega20_ih_init_register_offset()
61 		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);  in vega20_ih_init_register_offset()
62 		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);  in vega20_ih_init_register_offset()
63 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);  in vega20_ih_init_register_offset()
64 		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);  in vega20_ih_init_register_offset()
65 		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);  in vega20_ih_init_register_offset()
66 		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);  in vega20_ih_init_register_offset()
67 		ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);  in vega20_ih_init_register_offset()
68 		ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);  in vega20_ih_init_register_offset()
69 		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;  in vega20_ih_init_register_offset()
73 		ih_regs = &adev->irq.ih1.ih_regs;  in vega20_ih_init_register_offset()
74 		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);  in vega20_ih_init_register_offset()
75 		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);  in vega20_ih_init_register_offset()
76 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);  in vega20_ih_init_register_offset()
77 		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);  in vega20_ih_init_register_offset()
78 		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);  in vega20_ih_init_register_offset()
79 		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);  in vega20_ih_init_register_offset()
80 		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;  in vega20_ih_init_register_offset()
84 		ih_regs = &adev->irq.ih2.ih_regs;  in vega20_ih_init_register_offset()
85 		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);  in vega20_ih_init_register_offset()
86 		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);  in vega20_ih_init_register_offset()
87 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);  in vega20_ih_init_register_offset()
88 		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);  in vega20_ih_init_register_offset()
89 		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);  in vega20_ih_init_register_offset()
90 		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);  in vega20_ih_init_register_offset()
91 		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;  in vega20_ih_init_register_offset()
108 	struct amdgpu_ih_regs *ih_regs;  in vega20_ih_toggle_ring_interrupts()  local
111 	ih_regs = &ih->ih_regs;  in vega20_ih_toggle_ring_interrupts()
113 	tmp = RREG32(ih_regs->ih_rb_cntl);  in vega20_ih_toggle_ring_interrupts()
121 		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {  in vega20_ih_toggle_ring_interrupts()
126 		WREG32(ih_regs->ih_rb_cntl, tmp);  in vega20_ih_toggle_ring_interrupts()
133 		WREG32(ih_regs->ih_rb_rptr, 0);  in vega20_ih_toggle_ring_interrupts()
134 		WREG32(ih_regs->ih_rb_wptr, 0);  in vega20_ih_toggle_ring_interrupts()
220 	struct amdgpu_ih_regs *ih_regs;  in vega20_ih_enable_ring()  local
223 	ih_regs = &ih->ih_regs;  in vega20_ih_enable_ring()
226 	WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);  in vega20_ih_enable_ring()
227 	WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);  in vega20_ih_enable_ring()
229 	tmp = RREG32(ih_regs->ih_rb_cntl);  in vega20_ih_enable_ring()
236 		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {  in vega20_ih_enable_ring()
241 		WREG32(ih_regs->ih_rb_cntl, tmp);  in vega20_ih_enable_ring()
246 		WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));  in vega20_ih_enable_ring()
247 		WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);  in vega20_ih_enable_ring()
251 	WREG32(ih_regs->ih_rb_wptr, 0);  in vega20_ih_enable_ring()
252 	WREG32(ih_regs->ih_rb_rptr, 0);  in vega20_ih_enable_ring()
254 	WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih));  in vega20_ih_enable_ring()
387 	struct amdgpu_ih_regs *ih_regs;  in vega20_ih_get_wptr()  local
401 	ih_regs = &ih->ih_regs;  in vega20_ih_get_wptr()
404 	wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);  in vega20_ih_get_wptr()
420 	tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);  in vega20_ih_get_wptr()
422 	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);  in vega20_ih_get_wptr()
428 	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);  in vega20_ih_get_wptr()
446 	struct amdgpu_ih_regs *ih_regs;  in vega20_ih_irq_rearm()  local
448 	ih_regs = &ih->ih_regs;  in vega20_ih_irq_rearm()
452 		v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);  in vega20_ih_irq_rearm()
471 	struct amdgpu_ih_regs *ih_regs;  in vega20_ih_set_rptr()  local
484 		ih_regs = &ih->ih_regs;  in vega20_ih_set_rptr()
485 		WREG32(ih_regs->ih_rb_rptr, ih->rptr);  in vega20_ih_set_rptr()