63 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);  in vega20_ih_init_register_offset()
76 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);  in vega20_ih_init_register_offset()
87 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);  in vega20_ih_init_register_offset()
113 	tmp = RREG32(ih_regs->ih_rb_cntl);  in vega20_ih_toggle_ring_interrupts()
126 		WREG32(ih_regs->ih_rb_cntl, tmp);  in vega20_ih_toggle_ring_interrupts()
167 static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)  in vega20_ih_rb_cntl()  argument
171 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,  in vega20_ih_rb_cntl()
173 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,  in vega20_ih_rb_cntl()
175 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,  in vega20_ih_rb_cntl()
177 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);  in vega20_ih_rb_cntl()
181 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,  in vega20_ih_rb_cntl()
183 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);  in vega20_ih_rb_cntl()
184 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);  in vega20_ih_rb_cntl()
185 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);  in vega20_ih_rb_cntl()
187 	return ih_rb_cntl;  in vega20_ih_rb_cntl()
229 	tmp = RREG32(ih_regs->ih_rb_cntl);  in vega20_ih_enable_ring()
241 		WREG32(ih_regs->ih_rb_cntl, tmp);  in vega20_ih_enable_ring()
420 	tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);  in vega20_ih_get_wptr()
422 	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);  in vega20_ih_get_wptr()
428 	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);  in vega20_ih_get_wptr()