49 	struct amdgpu_ih_regs *ih_regs;  in vega10_ih_init_register_offset()  local
52 		ih_regs = &adev->irq.ih.ih_regs;  in vega10_ih_init_register_offset()
53 		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);  in vega10_ih_init_register_offset()
54 		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);  in vega10_ih_init_register_offset()
55 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);  in vega10_ih_init_register_offset()
56 		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);  in vega10_ih_init_register_offset()
57 		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);  in vega10_ih_init_register_offset()
58 		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);  in vega10_ih_init_register_offset()
59 		ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);  in vega10_ih_init_register_offset()
60 		ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);  in vega10_ih_init_register_offset()
61 		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;  in vega10_ih_init_register_offset()
65 		ih_regs = &adev->irq.ih1.ih_regs;  in vega10_ih_init_register_offset()
66 		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);  in vega10_ih_init_register_offset()
67 		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);  in vega10_ih_init_register_offset()
68 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);  in vega10_ih_init_register_offset()
69 		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);  in vega10_ih_init_register_offset()
70 		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);  in vega10_ih_init_register_offset()
71 		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);  in vega10_ih_init_register_offset()
72 		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;  in vega10_ih_init_register_offset()
76 		ih_regs = &adev->irq.ih2.ih_regs;  in vega10_ih_init_register_offset()
77 		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);  in vega10_ih_init_register_offset()
78 		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);  in vega10_ih_init_register_offset()
79 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);  in vega10_ih_init_register_offset()
80 		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);  in vega10_ih_init_register_offset()
81 		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);  in vega10_ih_init_register_offset()
82 		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);  in vega10_ih_init_register_offset()
83 		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;  in vega10_ih_init_register_offset()
100 	struct amdgpu_ih_regs *ih_regs;  in vega10_ih_toggle_ring_interrupts()  local
103 	ih_regs = &ih->ih_regs;  in vega10_ih_toggle_ring_interrupts()
105 	tmp = RREG32(ih_regs->ih_rb_cntl);  in vega10_ih_toggle_ring_interrupts()
112 		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {  in vega10_ih_toggle_ring_interrupts()
117 		WREG32(ih_regs->ih_rb_cntl, tmp);  in vega10_ih_toggle_ring_interrupts()
124 		WREG32(ih_regs->ih_rb_rptr, 0);  in vega10_ih_toggle_ring_interrupts()
125 		WREG32(ih_regs->ih_rb_wptr, 0);  in vega10_ih_toggle_ring_interrupts()
211 	struct amdgpu_ih_regs *ih_regs;  in vega10_ih_enable_ring()  local
214 	ih_regs = &ih->ih_regs;  in vega10_ih_enable_ring()
217 	WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);  in vega10_ih_enable_ring()
218 	WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);  in vega10_ih_enable_ring()
220 	tmp = RREG32(ih_regs->ih_rb_cntl);  in vega10_ih_enable_ring()
227 		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {  in vega10_ih_enable_ring()
232 		WREG32(ih_regs->ih_rb_cntl, tmp);  in vega10_ih_enable_ring()
237 		WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));  in vega10_ih_enable_ring()
238 		WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);  in vega10_ih_enable_ring()
242 	WREG32(ih_regs->ih_rb_wptr, 0);  in vega10_ih_enable_ring()
243 	WREG32(ih_regs->ih_rb_rptr, 0);  in vega10_ih_enable_ring()
245 	WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih));  in vega10_ih_enable_ring()
339 	struct amdgpu_ih_regs *ih_regs;  in vega10_ih_get_wptr()  local
353 	ih_regs = &ih->ih_regs;  in vega10_ih_get_wptr()
356 	wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);  in vega10_ih_get_wptr()
372 	tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);  in vega10_ih_get_wptr()
374 	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);  in vega10_ih_get_wptr()
380 	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);  in vega10_ih_get_wptr()
398 	struct amdgpu_ih_regs *ih_regs;  in vega10_ih_irq_rearm()  local
400 	ih_regs = &ih->ih_regs;  in vega10_ih_irq_rearm()
403 		v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);  in vega10_ih_irq_rearm()
422 	struct amdgpu_ih_regs *ih_regs;  in vega10_ih_set_rptr()  local
435 		ih_regs = &ih->ih_regs;  in vega10_ih_set_rptr()
436 		WREG32(ih_regs->ih_rb_rptr, ih->rptr);  in vega10_ih_set_rptr()