55 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);  in vega10_ih_init_register_offset()
68 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);  in vega10_ih_init_register_offset()
79 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);  in vega10_ih_init_register_offset()
105 	tmp = RREG32(ih_regs->ih_rb_cntl);  in vega10_ih_toggle_ring_interrupts()
117 		WREG32(ih_regs->ih_rb_cntl, tmp);  in vega10_ih_toggle_ring_interrupts()
158 static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)  in vega10_ih_rb_cntl()  argument
162 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,  in vega10_ih_rb_cntl()
164 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,  in vega10_ih_rb_cntl()
166 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,  in vega10_ih_rb_cntl()
168 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);  in vega10_ih_rb_cntl()
172 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,  in vega10_ih_rb_cntl()
174 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);  in vega10_ih_rb_cntl()
175 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);  in vega10_ih_rb_cntl()
176 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);  in vega10_ih_rb_cntl()
178 	return ih_rb_cntl;  in vega10_ih_rb_cntl()
220 	tmp = RREG32(ih_regs->ih_rb_cntl);  in vega10_ih_enable_ring()
232 		WREG32(ih_regs->ih_rb_cntl, tmp);  in vega10_ih_enable_ring()
372 	tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);  in vega10_ih_get_wptr()
374 	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);  in vega10_ih_get_wptr()
380 	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);  in vega10_ih_get_wptr()