Lines Matching refs:indirect
498 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v3_0_mc_resume_dpg_mode() argument
505 if (!indirect) { in vcn_v3_0_mc_resume_dpg_mode()
508 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
511 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
513 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
516 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
518 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
520 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
526 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
529 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
533 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
536 if (!indirect) in vcn_v3_0_mc_resume_dpg_mode()
538 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
541 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
544 if (!indirect) { in vcn_v3_0_mc_resume_dpg_mode()
547 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
550 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
552 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
555 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
557 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
559 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
562 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
567 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
570 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
572 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
574 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
579 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
582 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
584 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
587 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
591 UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
827 uint8_t sram_sel, int inst_idx, uint8_t indirect) in vcn_v3_0_clock_gating_dpg_mode() argument
859 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
863 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
867 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
871 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
942 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v3_0_start_dpg_mode() argument
957 if (indirect) in vcn_v3_0_start_dpg_mode()
961 vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); in vcn_v3_0_start_dpg_mode()
968 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
972 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v3_0_start_dpg_mode()
984 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
988 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); in vcn_v3_0_start_dpg_mode()
995 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); in vcn_v3_0_start_dpg_mode()
1002 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); in vcn_v3_0_start_dpg_mode()
1008 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); in vcn_v3_0_start_dpg_mode()
1010 vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect); in vcn_v3_0_start_dpg_mode()
1013 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); in vcn_v3_0_start_dpg_mode()
1015 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); in vcn_v3_0_start_dpg_mode()
1019 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); in vcn_v3_0_start_dpg_mode()
1023 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); in vcn_v3_0_start_dpg_mode()
1028 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
1033 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); in vcn_v3_0_start_dpg_mode()
1037 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
1039 if (indirect) in vcn_v3_0_start_dpg_mode()