Lines Matching refs:indirect
469 static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v2_5_mc_resume_dpg_mode() argument
476 if (!indirect) { in vcn_v2_5_mc_resume_dpg_mode()
479 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
482 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
484 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
487 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
489 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
491 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
497 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
500 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
504 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
507 if (!indirect) in vcn_v2_5_mc_resume_dpg_mode()
509 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
512 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
515 if (!indirect) { in vcn_v2_5_mc_resume_dpg_mode()
518 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
521 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
523 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
526 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
528 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
530 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
533 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
538 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
541 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
543 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
545 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
550 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
553 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
555 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
558 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
562 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
683 uint8_t sram_sel, int inst_idx, uint8_t indirect) in vcn_v2_5_clock_gating_dpg_mode() argument
715 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
719 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
723 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
727 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
793 bool indirect) in vcn_v2_6_enable_ras() argument
806 tmp, 0, indirect); in vcn_v2_6_enable_ras()
811 tmp, 0, indirect); in vcn_v2_6_enable_ras()
816 tmp, 0, indirect); in vcn_v2_6_enable_ras()
819 static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v2_5_start_dpg_mode() argument
834 if (indirect) in vcn_v2_5_start_dpg_mode()
838 vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); in vcn_v2_5_start_dpg_mode()
845 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
849 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
861 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
865 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); in vcn_v2_5_start_dpg_mode()
872 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); in vcn_v2_5_start_dpg_mode()
879 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); in vcn_v2_5_start_dpg_mode()
885 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); in vcn_v2_5_start_dpg_mode()
887 vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect); in vcn_v2_5_start_dpg_mode()
890 VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); in vcn_v2_5_start_dpg_mode()
892 VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); in vcn_v2_5_start_dpg_mode()
896 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
898 vcn_v2_6_enable_ras(adev, inst_idx, indirect); in vcn_v2_5_start_dpg_mode()
902 VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
907 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
912 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); in vcn_v2_5_start_dpg_mode()
914 if (indirect) in vcn_v2_5_start_dpg_mode()