Lines Matching +full:0 +full:x431
40 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00
41 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200
43 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27
44 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f
45 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10
46 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11
47 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29
48 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66
49 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d
51 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431
52 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4
53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5
54 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c
87 adev->vcn.harvest_config = 0; in vcn_v2_5_early_init()
93 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_early_init()
127 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { in vcn_v2_5_sw_init()
137 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_5_sw_init()
161 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { in vcn_v2_5_sw_init()
190 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0)) in vcn_v2_5_sw_init()
191 ring->vm_hub = AMDGPU_MMHUB1(0); in vcn_v2_5_sw_init()
193 ring->vm_hub = AMDGPU_MMHUB0(0); in vcn_v2_5_sw_init()
197 0, AMDGPU_RING_PRIO_DEFAULT, NULL); in vcn_v2_5_sw_init()
201 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_5_sw_init()
210 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0)) in vcn_v2_5_sw_init()
211 ring->vm_hub = AMDGPU_MMHUB1(0); in vcn_v2_5_sw_init()
213 ring->vm_hub = AMDGPU_MMHUB0(0); in vcn_v2_5_sw_init()
217 &adev->vcn.inst[j].irq, 0, in vcn_v2_5_sw_init()
243 return 0; in vcn_v2_5_sw_init()
260 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_sw_fini()
264 fw_shared->present_flag_0 = 0; in vcn_v2_5_sw_fini()
293 int i, j, r = 0; in vcn_v2_5_hw_init()
298 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in vcn_v2_5_hw_init()
303 adev->vcn.inst[j].ring_enc[0].sched.ready = true; in vcn_v2_5_hw_init()
318 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_5_hw_init()
349 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_hw_fini()
359 amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0); in vcn_v2_5_hw_fini()
362 return 0; in vcn_v2_5_hw_fini()
420 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_mc_resume()
423 /* cache window 0: fw */ in vcn_v2_5_mc_resume()
429 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_5_mc_resume()
430 offset = 0; in vcn_v2_5_mc_resume()
447 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v2_5_mc_resume()
455 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v2_5_mc_resume()
463 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0); in vcn_v2_5_mc_resume()
474 /* cache window 0: fw */ in vcn_v2_5_mc_resume_dpg_mode()
478 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
479 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
481 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
482 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
484 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
487 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
489 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
491 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
493 offset = 0; in vcn_v2_5_mc_resume_dpg_mode()
496 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
497 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
499 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
500 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
503 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_5_mc_resume_dpg_mode()
504 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
509 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
512 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
517 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
518 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
520 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
521 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
523 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
526 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
528 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
530 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
533 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
537 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
538 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
540 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
541 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
543 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
545 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
549 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
550 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
552 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
553 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
555 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
557 VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0), in vcn_v2_5_mc_resume_dpg_mode()
558 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
562 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
577 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_disable_clock_gating()
614 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v2_5_disable_clock_gating()
685 uint32_t reg_data = 0; in vcn_v2_5_clock_gating_dpg_mode()
691 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_clock_gating_dpg_mode()
715 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
719 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
723 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
727 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
739 uint32_t data = 0; in vcn_v2_5_enable_clock_gating()
742 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_enable_clock_gating()
750 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_enable_clock_gating()
797 if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(2, 6, 0)) in vcn_v2_6_enable_ras()
805 SOC15_DPG_MODE_OFFSET(VCN, 0, mmVCN_RAS_CNTL), in vcn_v2_6_enable_ras()
806 tmp, 0, indirect); in vcn_v2_6_enable_ras()
810 SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_VCPU_INT_EN), in vcn_v2_6_enable_ras()
811 tmp, 0, indirect); in vcn_v2_6_enable_ras()
815 SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_SYS_INT_EN), in vcn_v2_6_enable_ras()
816 tmp, 0, indirect); in vcn_v2_6_enable_ras()
838 vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); in vcn_v2_5_start_dpg_mode()
841 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); in vcn_v2_5_start_dpg_mode()
845 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
849 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
852 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | in vcn_v2_5_start_dpg_mode()
859 0x00100000L); in vcn_v2_5_start_dpg_mode()
861 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
864 VCN, 0, mmUVD_MPC_CNTL), in vcn_v2_5_start_dpg_mode()
865 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); in vcn_v2_5_start_dpg_mode()
868 VCN, 0, mmUVD_MPC_SET_MUXA0), in vcn_v2_5_start_dpg_mode()
869 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v2_5_start_dpg_mode()
870 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v2_5_start_dpg_mode()
871 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | in vcn_v2_5_start_dpg_mode()
872 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); in vcn_v2_5_start_dpg_mode()
875 VCN, 0, mmUVD_MPC_SET_MUXB0), in vcn_v2_5_start_dpg_mode()
876 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | in vcn_v2_5_start_dpg_mode()
877 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v2_5_start_dpg_mode()
878 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v2_5_start_dpg_mode()
879 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); in vcn_v2_5_start_dpg_mode()
882 VCN, 0, mmUVD_MPC_SET_MUX), in vcn_v2_5_start_dpg_mode()
883 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v2_5_start_dpg_mode()
884 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v2_5_start_dpg_mode()
885 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); in vcn_v2_5_start_dpg_mode()
890 VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); in vcn_v2_5_start_dpg_mode()
892 VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); in vcn_v2_5_start_dpg_mode()
896 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
902 VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
904 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); in vcn_v2_5_start_dpg_mode()
907 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
911 VCN, 0, mmUVD_MASTINT_EN), in vcn_v2_5_start_dpg_mode()
912 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); in vcn_v2_5_start_dpg_mode()
915 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); in vcn_v2_5_start_dpg_mode()
920 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start_dpg_mode()
934 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); in vcn_v2_5_start_dpg_mode()
947 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); in vcn_v2_5_start_dpg_mode()
949 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); in vcn_v2_5_start_dpg_mode()
958 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); in vcn_v2_5_start_dpg_mode()
960 return 0; in vcn_v2_5_start_dpg_mode()
972 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_start()
981 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, in vcn_v2_5_start()
990 return 0; in vcn_v2_5_start()
995 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_start()
1003 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, in vcn_v2_5_start()
1008 tmp &= ~0xff; in vcn_v2_5_start()
1009 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8| in vcn_v2_5_start()
1018 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; in vcn_v2_5_start()
1023 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v2_5_start()
1024 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v2_5_start()
1025 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | in vcn_v2_5_start()
1026 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); in vcn_v2_5_start()
1030 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | in vcn_v2_5_start()
1031 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v2_5_start()
1032 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v2_5_start()
1033 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); in vcn_v2_5_start()
1037 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v2_5_start()
1038 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v2_5_start()
1039 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); in vcn_v2_5_start()
1044 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_start()
1055 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, in vcn_v2_5_start()
1059 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, in vcn_v2_5_start()
1062 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_start()
1065 for (k = 0; k < 10; ++k) { in vcn_v2_5_start()
1068 for (j = 0; j < 100; ++j) { in vcn_v2_5_start()
1077 r = 0; in vcn_v2_5_start()
1086 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_start()
1104 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, in vcn_v2_5_start()
1107 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); in vcn_v2_5_start()
1112 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start()
1127 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); in vcn_v2_5_start()
1135 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v2_5_start()
1153 return 0; in vcn_v2_5_start()
1159 uint32_t data = 0, loop = 0, size = 0; in vcn_v2_5_mmsch_start()
1170 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); in vcn_v2_5_mmsch_start()
1171 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); in vcn_v2_5_mmsch_start()
1174 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); in vcn_v2_5_mmsch_start()
1177 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); in vcn_v2_5_mmsch_start()
1178 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, data); in vcn_v2_5_mmsch_start()
1181 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); in vcn_v2_5_mmsch_start()
1184 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); in vcn_v2_5_mmsch_start()
1190 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001); in vcn_v2_5_mmsch_start()
1192 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_5_mmsch_start()
1194 while ((data & 0x10000002) != 0x10000002) { in vcn_v2_5_mmsch_start()
1196 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_5_mmsch_start()
1209 return 0; in vcn_v2_5_mmsch_start()
1216 uint32_t table_size = 0; in vcn_v2_5_sriov_start()
1217 struct mmsch_v1_0_cmd_direct_write direct_wt = { { 0 } }; in vcn_v2_5_sriov_start()
1218 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { { 0 } }; in vcn_v2_5_sriov_start()
1219 struct mmsch_v1_0_cmd_end end = { { 0 } }; in vcn_v2_5_sriov_start()
1231 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_sriov_start()
1233 header->eng[i].init_status = 0; in vcn_v2_5_sriov_start()
1234 header->eng[i].table_size = 0; in vcn_v2_5_sriov_start()
1236 table_size = 0; in vcn_v2_5_sriov_start()
1253 offset = 0; in vcn_v2_5_sriov_start()
1255 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0); in vcn_v2_5_sriov_start()
1284 0); in vcn_v2_5_sriov_start()
1300 0); in vcn_v2_5_sriov_start()
1305 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v2_5_sriov_start()
1306 ring->wptr = 0; in vcn_v2_5_sriov_start()
1319 ring->wptr = 0; in vcn_v2_5_sriov_start()
1331 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_sriov_start()
1362 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1365 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1367 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; in vcn_v2_5_stop_dpg_mode()
1368 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1374 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, in vcn_v2_5_stop_dpg_mode()
1377 return 0; in vcn_v2_5_stop_dpg_mode()
1383 int i, r = 0; in vcn_v2_5_stop()
1385 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_stop()
1394 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_5_stop()
1428 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_stop()
1432 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); in vcn_v2_5_stop()
1445 return 0; in vcn_v2_5_stop()
1452 uint32_t reg_data = 0; in vcn_v2_5_pause_dpg_mode()
1453 int ret_code = 0; in vcn_v2_5_pause_dpg_mode()
1463 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, in vcn_v2_5_pause_dpg_mode()
1485 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; in vcn_v2_5_pause_dpg_mode()
1486 ring->wptr = 0; in vcn_v2_5_pause_dpg_mode()
1496 ring->wptr = 0; in vcn_v2_5_pause_dpg_mode()
1506 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); in vcn_v2_5_pause_dpg_mode()
1514 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, in vcn_v2_5_pause_dpg_mode()
1520 return 0; in vcn_v2_5_pause_dpg_mode()
1575 .align_mask = 0xf,
1614 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) in vcn_v2_5_enc_ring_get_rptr()
1631 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { in vcn_v2_5_enc_ring_get_wptr()
1655 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { in vcn_v2_5_enc_ring_set_wptr()
1674 .align_mask = 0x3f,
1705 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_set_dec_ring_funcs()
1718 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in vcn_v2_5_set_enc_ring_funcs()
1721 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_5_set_enc_ring_funcs()
1734 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_is_idle()
1746 int i, ret = 0; in vcn_v2_5_wait_for_idle()
1748 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_wait_for_idle()
1767 return 0; in vcn_v2_5_set_clockgating_state()
1777 return 0; in vcn_v2_5_set_clockgating_state()
1787 return 0; in vcn_v2_5_set_powergating_state()
1790 return 0; in vcn_v2_5_set_powergating_state()
1808 return 0; in vcn_v2_5_set_interrupt_state()
1816 return 0; in vcn_v2_6_set_ras_interrupt_state()
1827 ip_instance = 0; in vcn_v2_5_process_interrupt()
1834 return 0; in vcn_v2_5_process_interrupt()
1844 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); in vcn_v2_5_process_interrupt()
1851 entry->src_id, entry->src_data[0]); in vcn_v2_5_process_interrupt()
1855 return 0; in vcn_v2_5_process_interrupt()
1872 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_set_irq_funcs()
1928 .rev = 0,
1937 .rev = 0,
1944 uint32_t poison_stat = 0, reg_value = 0; in vcn_v2_6_query_poison_by_instance()
1965 uint32_t poison_stat = 0; in vcn_v2_6_query_poison_status()
1967 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) in vcn_v2_6_query_poison_status()
1968 for (sub = 0; sub < AMDGPU_VCN_V2_6_MAX_SUB_BLOCK; sub++) in vcn_v2_6_query_poison_status()
1988 switch (adev->ip_versions[VCN_HWIP][0]) { in vcn_v2_5_set_ras_funcs()
1989 case IP_VERSION(2, 6, 0): in vcn_v2_5_set_ras_funcs()