140 	adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
141 	adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
142 	adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
143 	adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
144 	adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
145 	adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
147 	adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
149 	adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
151 	adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
153 	adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
155 	adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
1382 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));  in vcn_v2_0_dec_ring_insert_start()
1384 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));  in vcn_v2_0_dec_ring_insert_start()
1399 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));  in vcn_v2_0_dec_ring_insert_end()
1419 		amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0));  in vcn_v2_0_dec_ring_insert_nop()
1440 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0));  in vcn_v2_0_dec_ring_emit_fence()
1443 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));  in vcn_v2_0_dec_ring_emit_fence()
1446 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));  in vcn_v2_0_dec_ring_emit_fence()
1449 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));  in vcn_v2_0_dec_ring_emit_fence()
1452 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));  in vcn_v2_0_dec_ring_emit_fence()
1455 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));  in vcn_v2_0_dec_ring_emit_fence()
1458 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));  in vcn_v2_0_dec_ring_emit_fence()
1481 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0));  in vcn_v2_0_dec_ring_emit_ib()
1484 	amdgpu_ring_write(ring,	PACKET0(adev->vcn.internal.ib_bar_low, 0));  in vcn_v2_0_dec_ring_emit_ib()
1486 	amdgpu_ring_write(ring,	PACKET0(adev->vcn.internal.ib_bar_high, 0));  in vcn_v2_0_dec_ring_emit_ib()
1488 	amdgpu_ring_write(ring,	PACKET0(adev->vcn.internal.ib_size, 0));  in vcn_v2_0_dec_ring_emit_ib()
1497 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));  in vcn_v2_0_dec_ring_emit_reg_wait()
1500 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));  in vcn_v2_0_dec_ring_emit_reg_wait()
1503 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0));  in vcn_v2_0_dec_ring_emit_reg_wait()
1506 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));  in vcn_v2_0_dec_ring_emit_reg_wait()
1531 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));  in vcn_v2_0_dec_ring_emit_wreg()
1534 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));  in vcn_v2_0_dec_ring_emit_wreg()
1537 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));  in vcn_v2_0_dec_ring_emit_wreg()
1738 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));  in vcn_v2_0_dec_ring_test_ring()
1740 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));  in vcn_v2_0_dec_ring_test_ring()