85 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));  in vce_v3_0_ring_get_rptr()
87 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));  in vce_v3_0_ring_get_rptr()
96 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);  in vce_v3_0_ring_get_rptr()
117 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));  in vce_v3_0_ring_get_wptr()
119 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));  in vce_v3_0_ring_get_wptr()
128 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);  in vce_v3_0_ring_get_wptr()
148 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));  in vce_v3_0_ring_set_wptr()
150 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));  in vce_v3_0_ring_set_wptr()
153 		WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));  in vce_v3_0_ring_set_wptr()
155 		WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));  in vce_v3_0_ring_set_wptr()
157 		WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));  in vce_v3_0_ring_set_wptr()
159 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);  in vce_v3_0_ring_set_wptr()
185 		WREG32(mmVCE_CLOCK_GATING_B, data);  in vce_v3_0_set_vce_sw_clock_gating()
190 		WREG32(mmVCE_UENC_CLOCK_GATING, data);  in vce_v3_0_set_vce_sw_clock_gating()
195 		WREG32(mmVCE_UENC_CLOCK_GATING_2, data);  in vce_v3_0_set_vce_sw_clock_gating()
199 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);  in vce_v3_0_set_vce_sw_clock_gating()
206 		WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);  in vce_v3_0_set_vce_sw_clock_gating()
211 		WREG32(mmVCE_CLOCK_GATING_B, data);  in vce_v3_0_set_vce_sw_clock_gating()
215 		WREG32(mmVCE_UENC_CLOCK_GATING, data);  in vce_v3_0_set_vce_sw_clock_gating()
219 		WREG32(mmVCE_UENC_CLOCK_GATING_2, data);  in vce_v3_0_set_vce_sw_clock_gating()
223 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);  in vce_v3_0_set_vce_sw_clock_gating()
230 		WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);  in vce_v3_0_set_vce_sw_clock_gating()
275 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));  in vce_v3_0_start()
281 			WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));  in vce_v3_0_start()
282 			WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));  in vce_v3_0_start()
283 			WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);  in vce_v3_0_start()
284 			WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vce_v3_0_start()
285 			WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);  in vce_v3_0_start()
288 			WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));  in vce_v3_0_start()
289 			WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));  in vce_v3_0_start()
290 			WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);  in vce_v3_0_start()
291 			WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vce_v3_0_start()
292 			WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);  in vce_v3_0_start()
295 			WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr));  in vce_v3_0_start()
296 			WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));  in vce_v3_0_start()
297 			WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr);  in vce_v3_0_start()
298 			WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));  in vce_v3_0_start()
299 			WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4);  in vce_v3_0_start()
325 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);  in vce_v3_0_start()
340 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));  in vce_v3_0_stop()
351 		WREG32(mmVCE_STATUS, 0);  in vce_v3_0_stop()
354 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);  in vce_v3_0_stop()
559 	WREG32(mmVCE_CLOCK_GATING_B, 0x1FF);  in vce_v3_0_mc_resume()
561 	WREG32(mmVCE_LMI_CTRL, 0x00398000);  in vce_v3_0_mc_resume()
563 	WREG32(mmVCE_LMI_SWAP_CNTL, 0);  in vce_v3_0_mc_resume()
564 	WREG32(mmVCE_LMI_SWAP_CNTL1, 0);  in vce_v3_0_mc_resume()
565 	WREG32(mmVCE_LMI_VM_CTRL, 0);  in vce_v3_0_mc_resume()
569 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));  in vce_v3_0_mc_resume()
570 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));  in vce_v3_0_mc_resume()
571 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8));  in vce_v3_0_mc_resume()
573 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));  in vce_v3_0_mc_resume()
576 	WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);  in vce_v3_0_mc_resume()
577 	WREG32(mmVCE_VCPU_CACHE_SIZE0, size);  in vce_v3_0_mc_resume()
582 		WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);  in vce_v3_0_mc_resume()
583 		WREG32(mmVCE_VCPU_CACHE_SIZE1, size);  in vce_v3_0_mc_resume()
586 		WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);  in vce_v3_0_mc_resume()
587 		WREG32(mmVCE_VCPU_CACHE_SIZE2, size);  in vce_v3_0_mc_resume()
591 		WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff);  in vce_v3_0_mc_resume()
592 		WREG32(mmVCE_VCPU_CACHE_SIZE1, size);  in vce_v3_0_mc_resume()
595 		WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0xfffffff);  in vce_v3_0_mc_resume()
596 		WREG32(mmVCE_VCPU_CACHE_SIZE2, size);  in vce_v3_0_mc_resume()
651 	WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));  in vce_v3_0_check_soft_reset()
656 	WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));  in vce_v3_0_check_soft_reset()
661 	WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));  in vce_v3_0_check_soft_reset()
688 		WREG32(mmSRBM_SOFT_RESET, tmp);  in vce_v3_0_soft_reset()
694 		WREG32(mmSRBM_SOFT_RESET, tmp);  in vce_v3_0_soft_reset()
782 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(i));  in vce_v3_0_set_clockgating_state()
789 			WREG32(mmVCE_CLOCK_GATING_A, data);  in vce_v3_0_set_clockgating_state()
795 			WREG32(mmVCE_UENC_CLOCK_GATING, data);  in vce_v3_0_set_clockgating_state()
801 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);  in vce_v3_0_set_clockgating_state()