94 		WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));  in vce_v2_0_ring_set_wptr()
96 		WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));  in vce_v2_0_ring_set_wptr()
144 	WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);  in vce_v2_0_disable_cg()
155 	WREG32(mmVCE_CLOCK_GATING_A, tmp);  in vce_v2_0_init_cg()
160 	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);  in vce_v2_0_init_cg()
165 	WREG32(mmVCE_CLOCK_GATING_B, tmp);  in vce_v2_0_init_cg()
175 	WREG32(mmVCE_CLOCK_GATING_B, 0xf7);  in vce_v2_0_mc_resume()
177 	WREG32(mmVCE_LMI_CTRL, 0x00398000);  in vce_v2_0_mc_resume()
179 	WREG32(mmVCE_LMI_SWAP_CNTL, 0);  in vce_v2_0_mc_resume()
180 	WREG32(mmVCE_LMI_SWAP_CNTL1, 0);  in vce_v2_0_mc_resume()
181 	WREG32(mmVCE_LMI_VM_CTRL, 0);  in vce_v2_0_mc_resume()
183 	WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));  in vce_v2_0_mc_resume()
187 	WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);  in vce_v2_0_mc_resume()
188 	WREG32(mmVCE_VCPU_CACHE_SIZE0, size);  in vce_v2_0_mc_resume()
192 	WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);  in vce_v2_0_mc_resume()
193 	WREG32(mmVCE_VCPU_CACHE_SIZE1, size);  in vce_v2_0_mc_resume()
197 	WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);  in vce_v2_0_mc_resume()
198 	WREG32(mmVCE_VCPU_CACHE_SIZE2, size);  in vce_v2_0_mc_resume()
244 	WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));  in vce_v2_0_start()
245 	WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));  in vce_v2_0_start()
246 	WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);  in vce_v2_0_start()
247 	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vce_v2_0_start()
248 	WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);  in vce_v2_0_start()
251 	WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));  in vce_v2_0_start()
252 	WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));  in vce_v2_0_start()
253 	WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);  in vce_v2_0_start()
254 	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vce_v2_0_start()
255 	WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);  in vce_v2_0_start()
305 	WREG32(mmVCE_STATUS, 0);  in vce_v2_0_stop()
317 		WREG32(mmVCE_CLOCK_GATING_B, tmp);  in vce_v2_0_set_sw_cg()
321 		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);  in vce_v2_0_set_sw_cg()
325 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);  in vce_v2_0_set_sw_cg()
327 		WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);  in vce_v2_0_set_sw_cg()
332 		WREG32(mmVCE_CLOCK_GATING_B, tmp);  in vce_v2_0_set_sw_cg()
337 		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);  in vce_v2_0_set_sw_cg()
341 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);  in vce_v2_0_set_sw_cg()
358 		WREG32(mmVCE_CLOCK_GATING_B, tmp);  in vce_v2_0_set_dyn_cg()
362 		WREG32(mmVCE_CLOCK_GATING_B, tmp);  in vce_v2_0_set_dyn_cg()
369 		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);  in vce_v2_0_set_dyn_cg()
374 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);  in vce_v2_0_set_dyn_cg()
377 	WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);  in vce_v2_0_set_dyn_cg()
380 		WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);  in vce_v2_0_set_dyn_cg()