551 			tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,  in uvd_v7_0_hw_init()
556 			tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,  in uvd_v7_0_hw_init()
561 			tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,  in uvd_v7_0_hw_init()
567 			amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,  in uvd_v7_0_hw_init()
571 			amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,  in uvd_v7_0_hw_init()
1185 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));  in uvd_v7_0_ring_emit_fence()
1188 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_ring_emit_fence()
1191 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_ring_emit_fence()
1194 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_ring_emit_fence()
1198 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_ring_emit_fence()
1201 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_ring_emit_fence()
1204 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_ring_emit_fence()
1261 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));  in uvd_v7_0_ring_test_ring()
1326 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0));  in uvd_v7_0_ring_emit_ib()
1330 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));  in uvd_v7_0_ring_emit_ib()
1333 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));  in uvd_v7_0_ring_emit_ib()
1336 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));  in uvd_v7_0_ring_emit_ib()
1370 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_ring_emit_wreg()
1373 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_ring_emit_wreg()
1376 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_ring_emit_wreg()
1386 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_ring_emit_reg_wait()
1389 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_ring_emit_reg_wait()
1392 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0));  in uvd_v7_0_ring_emit_reg_wait()
1395 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_ring_emit_reg_wait()
1422 		amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));  in uvd_v7_0_ring_insert_nop()