88 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));  in uvd_v5_0_ring_set_wptr()
282 	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,  in uvd_v5_0_mc_resume()
284 	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,  in uvd_v5_0_mc_resume()
289 	WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);  in uvd_v5_0_mc_resume()
290 	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);  in uvd_v5_0_mc_resume()
294 	WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);  in uvd_v5_0_mc_resume()
295 	WREG32(mmUVD_VCPU_CACHE_SIZE1, size);  in uvd_v5_0_mc_resume()
300 	WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);  in uvd_v5_0_mc_resume()
301 	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);  in uvd_v5_0_mc_resume()
303 	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in uvd_v5_0_mc_resume()
304 	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in uvd_v5_0_mc_resume()
305 	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in uvd_v5_0_mc_resume()
340 	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |  in uvd_v5_0_start()
352 	WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |  in uvd_v5_0_start()
360 	WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);  in uvd_v5_0_start()
361 	WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);  in uvd_v5_0_start()
363 	WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);  in uvd_v5_0_start()
364 	WREG32(mmUVD_MPC_SET_MUXA1, 0x0);  in uvd_v5_0_start()
365 	WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);  in uvd_v5_0_start()
366 	WREG32(mmUVD_MPC_SET_MUXB1, 0x0);  in uvd_v5_0_start()
367 	WREG32(mmUVD_MPC_SET_ALU, 0);  in uvd_v5_0_start()
368 	WREG32(mmUVD_MPC_SET_MUX, 0x88);  in uvd_v5_0_start()
371 	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);  in uvd_v5_0_start()
375 	WREG32(mmUVD_VCPU_CNTL,  1 << 9);  in uvd_v5_0_start()
381 	WREG32(mmUVD_SOFT_RESET, 0);  in uvd_v5_0_start()
424 	WREG32(mmUVD_RBC_RB_CNTL, tmp);  in uvd_v5_0_start()
427 	WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);  in uvd_v5_0_start()
430 	WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));  in uvd_v5_0_start()
433 	WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,  in uvd_v5_0_start()
435 	WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,  in uvd_v5_0_start()
439 	WREG32(mmUVD_RBC_RB_RPTR, 0);  in uvd_v5_0_start()
442 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));  in uvd_v5_0_start()
459 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);  in uvd_v5_0_stop()
466 	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);  in uvd_v5_0_stop()
470 	WREG32(mmUVD_VCPU_CNTL, 0x0);  in uvd_v5_0_stop()
475 	WREG32(mmUVD_STATUS, 0);  in uvd_v5_0_stop()
524 	WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);  in uvd_v5_0_ring_test_ring()
671 	WREG32(mmUVD_SUVD_CGC_GATE, data1);  in uvd_v5_0_enable_clock_gating()
672 	WREG32(mmUVD_CGC_GATE, data3);  in uvd_v5_0_enable_clock_gating()
718 	WREG32(mmUVD_CGC_CTRL, data);  in uvd_v5_0_set_sw_clock_gating()
719 	WREG32(mmUVD_SUVD_CGC_CTRL, data2);  in uvd_v5_0_set_sw_clock_gating()
758 	WREG32(mmUVD_CGC_GATE, data);
759 	WREG32(mmUVD_SUVD_CGC_GATE, data1);
776 			WREG32(mmUVD_CGC_CTRL, data);  in uvd_v5_0_enable_mgcg()
785 			WREG32(mmUVD_CGC_CTRL, data);  in uvd_v5_0_enable_mgcg()