51 	struct amdgpu_ih_regs *ih_regs;  in navi10_ih_init_register_offset()  local
54 		ih_regs = &adev->irq.ih.ih_regs;  in navi10_ih_init_register_offset()
55 		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);  in navi10_ih_init_register_offset()
56 		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);  in navi10_ih_init_register_offset()
57 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);  in navi10_ih_init_register_offset()
58 		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);  in navi10_ih_init_register_offset()
59 		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);  in navi10_ih_init_register_offset()
60 		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);  in navi10_ih_init_register_offset()
61 		ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);  in navi10_ih_init_register_offset()
62 		ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);  in navi10_ih_init_register_offset()
63 		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;  in navi10_ih_init_register_offset()
67 		ih_regs = &adev->irq.ih1.ih_regs;  in navi10_ih_init_register_offset()
68 		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);  in navi10_ih_init_register_offset()
69 		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);  in navi10_ih_init_register_offset()
70 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);  in navi10_ih_init_register_offset()
71 		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);  in navi10_ih_init_register_offset()
72 		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);  in navi10_ih_init_register_offset()
73 		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);  in navi10_ih_init_register_offset()
74 		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;  in navi10_ih_init_register_offset()
78 		ih_regs = &adev->irq.ih2.ih_regs;  in navi10_ih_init_register_offset()
79 		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);  in navi10_ih_init_register_offset()
80 		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);  in navi10_ih_init_register_offset()
81 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);  in navi10_ih_init_register_offset()
82 		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);  in navi10_ih_init_register_offset()
83 		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);  in navi10_ih_init_register_offset()
84 		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);  in navi10_ih_init_register_offset()
85 		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;  in navi10_ih_init_register_offset()
156 	struct amdgpu_ih_regs *ih_regs;  in navi10_ih_toggle_ring_interrupts()  local
159 	ih_regs = &ih->ih_regs;  in navi10_ih_toggle_ring_interrupts()
161 	tmp = RREG32(ih_regs->ih_rb_cntl);  in navi10_ih_toggle_ring_interrupts()
169 		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))  in navi10_ih_toggle_ring_interrupts()
172 		WREG32(ih_regs->ih_rb_cntl, tmp);  in navi10_ih_toggle_ring_interrupts()
179 		WREG32(ih_regs->ih_rb_rptr, 0);  in navi10_ih_toggle_ring_interrupts()
180 		WREG32(ih_regs->ih_rb_wptr, 0);  in navi10_ih_toggle_ring_interrupts()
266 	struct amdgpu_ih_regs *ih_regs;  in navi10_ih_enable_ring()  local
269 	ih_regs = &ih->ih_regs;  in navi10_ih_enable_ring()
272 	WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);  in navi10_ih_enable_ring()
273 	WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);  in navi10_ih_enable_ring()
275 	tmp = RREG32(ih_regs->ih_rb_cntl);  in navi10_ih_enable_ring()
283 		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {  in navi10_ih_enable_ring()
288 		WREG32(ih_regs->ih_rb_cntl, tmp);  in navi10_ih_enable_ring()
293 		WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));  in navi10_ih_enable_ring()
294 		WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);  in navi10_ih_enable_ring()
298 	WREG32(ih_regs->ih_rb_wptr, 0);  in navi10_ih_enable_ring()
299 	WREG32(ih_regs->ih_rb_rptr, 0);  in navi10_ih_enable_ring()
301 	WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih));  in navi10_ih_enable_ring()
410 	struct amdgpu_ih_regs *ih_regs;  in navi10_ih_get_wptr()  local
424 	ih_regs = &ih->ih_regs;  in navi10_ih_get_wptr()
427 	wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);  in navi10_ih_get_wptr()
442 	tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);  in navi10_ih_get_wptr()
444 	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);  in navi10_ih_get_wptr()
450 	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);  in navi10_ih_get_wptr()
467 	struct amdgpu_ih_regs *ih_regs;  in navi10_ih_irq_rearm()  local
469 	ih_regs = &ih->ih_regs;  in navi10_ih_irq_rearm()
473 		v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);  in navi10_ih_irq_rearm()
492 	struct amdgpu_ih_regs *ih_regs;  in navi10_ih_set_rptr()  local
505 		ih_regs = &ih->ih_regs;  in navi10_ih_set_rptr()
506 		WREG32(ih_regs->ih_rb_rptr, ih->rptr);  in navi10_ih_set_rptr()