57 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);  in navi10_ih_init_register_offset()
70 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);  in navi10_ih_init_register_offset()
81 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);  in navi10_ih_init_register_offset()
108 	u32 ih_cntl, ih_rb_cntl;  in force_update_wptr_for_self_int()  local
114 	ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);  in force_update_wptr_for_self_int()
120 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,  in force_update_wptr_for_self_int()
124 		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl))  in force_update_wptr_for_self_int()
127 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);  in force_update_wptr_for_self_int()
130 	ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);  in force_update_wptr_for_self_int()
131 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,  in force_update_wptr_for_self_int()
134 		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, ih_rb_cntl))  in force_update_wptr_for_self_int()
137 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);  in force_update_wptr_for_self_int()
161 	tmp = RREG32(ih_regs->ih_rb_cntl);  in navi10_ih_toggle_ring_interrupts()
172 		WREG32(ih_regs->ih_rb_cntl, tmp);  in navi10_ih_toggle_ring_interrupts()
213 static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)  in navi10_ih_rb_cntl()  argument
217 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,  in navi10_ih_rb_cntl()
219 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,  in navi10_ih_rb_cntl()
221 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,  in navi10_ih_rb_cntl()
223 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);  in navi10_ih_rb_cntl()
227 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,  in navi10_ih_rb_cntl()
229 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);  in navi10_ih_rb_cntl()
230 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);  in navi10_ih_rb_cntl()
231 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);  in navi10_ih_rb_cntl()
233 	return ih_rb_cntl;  in navi10_ih_rb_cntl()
275 	tmp = RREG32(ih_regs->ih_rb_cntl);  in navi10_ih_enable_ring()
288 		WREG32(ih_regs->ih_rb_cntl, tmp);  in navi10_ih_enable_ring()
442 	tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);  in navi10_ih_get_wptr()
444 	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);  in navi10_ih_get_wptr()
450 	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);  in navi10_ih_get_wptr()