56 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL);  in ih_v6_1_init_register_offset()
69 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1);  in ih_v6_1_init_register_offset()
96 	u32 ih_cntl, ih_rb_cntl;  in force_update_wptr_for_self_int()  local
99 	ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1);  in force_update_wptr_for_self_int()
105 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,  in force_update_wptr_for_self_int()
109 		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl))  in force_update_wptr_for_self_int()
112 		WREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1, ih_rb_cntl);  in force_update_wptr_for_self_int()
136 	tmp = RREG32(ih_regs->ih_rb_cntl);  in ih_v6_1_toggle_ring_interrupts()
146 		WREG32(ih_regs->ih_rb_cntl, tmp);  in ih_v6_1_toggle_ring_interrupts()
187 static uint32_t ih_v6_1_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)  in ih_v6_1_rb_cntl()  argument
191 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,  in ih_v6_1_rb_cntl()
193 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,  in ih_v6_1_rb_cntl()
195 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,  in ih_v6_1_rb_cntl()
197 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);  in ih_v6_1_rb_cntl()
201 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,  in ih_v6_1_rb_cntl()
203 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);  in ih_v6_1_rb_cntl()
204 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);  in ih_v6_1_rb_cntl()
205 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);  in ih_v6_1_rb_cntl()
207 	return ih_rb_cntl;  in ih_v6_1_rb_cntl()
249 	tmp = RREG32(ih_regs->ih_rb_cntl);  in ih_v6_1_enable_ring()
264 		WREG32(ih_regs->ih_rb_cntl, tmp);  in ih_v6_1_enable_ring()
418 	tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);  in ih_v6_1_get_wptr()
420 	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);  in ih_v6_1_get_wptr()
426 	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);  in ih_v6_1_get_wptr()