69 	adev->irq.ih.enabled = true;  in iceland_ih_enable_interrupts()
91 	adev->irq.ih.enabled = false;  in iceland_ih_disable_interrupts()
92 	adev->irq.ih.rptr = 0;  in iceland_ih_disable_interrupts()
108 	struct amdgpu_ih_ring *ih = &adev->irq.ih;  in iceland_ih_irq_init()  local
127 	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);  in iceland_ih_irq_init()
129 	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);  in iceland_ih_irq_init()
138 	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));  in iceland_ih_irq_init()
139 	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);  in iceland_ih_irq_init()
191 			       struct amdgpu_ih_ring *ih)  in iceland_ih_get_wptr()  argument
195 	wptr = le32_to_cpu(*ih->wptr_cpu);  in iceland_ih_get_wptr()
212 		wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);  in iceland_ih_get_wptr()
213 	ih->rptr = (wptr + 16) & ih->ptr_mask;  in iceland_ih_get_wptr()
225 	return (wptr & ih->ptr_mask);  in iceland_ih_get_wptr()
239 				 struct amdgpu_ih_ring *ih,  in iceland_ih_decode_iv()  argument
243 	u32 ring_index = ih->rptr >> 2;  in iceland_ih_decode_iv()
246 	dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);  in iceland_ih_decode_iv()
247 	dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);  in iceland_ih_decode_iv()
248 	dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);  in iceland_ih_decode_iv()
249 	dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);  in iceland_ih_decode_iv()
259 	ih->rptr += 16;  in iceland_ih_decode_iv()
271 				struct amdgpu_ih_ring *ih)  in iceland_ih_set_rptr()  argument
273 	WREG32(mmIH_RB_RPTR, ih->rptr);  in iceland_ih_set_rptr()
295 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);  in iceland_ih_sw_init()