44 		WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);  in hdp_v5_0_invalidate_hdp()
47 					HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);  in hdp_v5_0_invalidate_hdp()
62 	hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);  in hdp_v5_0_update_mem_power_gating()
63 	hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);  in hdp_v5_0_update_mem_power_gating()
71 	WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);  in hdp_v5_0_update_mem_power_gating()
91 	WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);  in hdp_v5_0_update_mem_power_gating()
133 			WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);  in hdp_v5_0_update_mem_power_gating()
142 	WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);  in hdp_v5_0_update_mem_power_gating()
153 	hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);  in hdp_v5_0_update_medium_grain_clock_gating()
173 	WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);  in hdp_v5_0_update_medium_grain_clock_gating()
189 	tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);  in hdp_v5_0_get_clockgating_state()
199 	tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);  in hdp_v5_0_get_clockgating_state()
212 	tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);  in hdp_v5_0_init_registers()
214 	WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);  in hdp_v5_0_init_registers()