Lines Matching refs:WREG32
179 WREG32(mmBIF_FB_EN, 0); in gmc_v8_0_mc_stop()
183 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); in gmc_v8_0_mc_stop()
196 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v8_0_mc_resume()
200 WREG32(mmBIF_FB_EN, tmp); in gmc_v8_0_mc_resume()
241 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, ixMC_IO_DEBUG_UP_159); in gmc_v8_0_init_microcode()
309 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
310 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v8_0_tonga_mc_load_microcode()
314 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); in gmc_v8_0_tonga_mc_load_microcode()
315 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); in gmc_v8_0_tonga_mc_load_microcode()
319 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); in gmc_v8_0_tonga_mc_load_microcode()
322 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
323 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v8_0_tonga_mc_load_microcode()
324 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v8_0_tonga_mc_load_microcode()
376 WREG32(mmMC_SEQ_MISC0, data); in gmc_v8_0_polaris_mc_load_microcode()
380 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); in gmc_v8_0_polaris_mc_load_microcode()
381 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); in gmc_v8_0_polaris_mc_load_microcode()
384 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_polaris_mc_load_microcode()
385 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v8_0_polaris_mc_load_microcode()
389 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); in gmc_v8_0_polaris_mc_load_microcode()
392 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_polaris_mc_load_microcode()
393 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v8_0_polaris_mc_load_microcode()
394 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v8_0_polaris_mc_load_microcode()
435 WREG32((0xb05 + j), 0x00000000); in gmc_v8_0_mc_program()
436 WREG32((0xb06 + j), 0x00000000); in gmc_v8_0_mc_program()
437 WREG32((0xb07 + j), 0x00000000); in gmc_v8_0_mc_program()
438 WREG32((0xb08 + j), 0x00000000); in gmc_v8_0_mc_program()
439 WREG32((0xb09 + j), 0x00000000); in gmc_v8_0_mc_program()
441 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); in gmc_v8_0_mc_program()
450 WREG32(mmVGA_HDP_CONTROL, tmp); in gmc_v8_0_mc_program()
455 WREG32(mmVGA_RENDER_CONTROL, tmp); in gmc_v8_0_mc_program()
458 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gmc_v8_0_mc_program()
460 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in gmc_v8_0_mc_program()
462 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, in gmc_v8_0_mc_program()
468 WREG32(mmMC_VM_FB_LOCATION, tmp); in gmc_v8_0_mc_program()
470 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); in gmc_v8_0_mc_program()
471 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); in gmc_v8_0_mc_program()
472 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); in gmc_v8_0_mc_program()
475 WREG32(mmMC_VM_AGP_BASE, 0); in gmc_v8_0_mc_program()
476 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); in gmc_v8_0_mc_program()
477 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); in gmc_v8_0_mc_program()
481 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); in gmc_v8_0_mc_program()
485 WREG32(mmHDP_MISC_CNTL, tmp); in gmc_v8_0_mc_program()
488 WREG32(mmHDP_HOST_PATH_CNTL, tmp); in gmc_v8_0_mc_program()
630 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v8_0_flush_gpu_tlb_pasid()
661 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v8_0_flush_gpu_tlb()
749 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_set_fault_enable_default()
782 WREG32(mmVM_PRT_CNTL, tmp); in gmc_v8_0_set_prt()
789 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); in gmc_v8_0_set_prt()
790 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); in gmc_v8_0_set_prt()
791 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); in gmc_v8_0_set_prt()
792 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); in gmc_v8_0_set_prt()
793 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); in gmc_v8_0_set_prt()
794 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); in gmc_v8_0_set_prt()
795 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); in gmc_v8_0_set_prt()
796 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); in gmc_v8_0_set_prt()
798 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); in gmc_v8_0_set_prt()
799 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); in gmc_v8_0_set_prt()
800 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); in gmc_v8_0_set_prt()
801 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); in gmc_v8_0_set_prt()
802 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); in gmc_v8_0_set_prt()
803 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); in gmc_v8_0_set_prt()
804 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); in gmc_v8_0_set_prt()
805 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); in gmc_v8_0_set_prt()
840 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v8_0_gart_enable()
850 WREG32(mmVM_L2_CNTL, tmp); in gmc_v8_0_gart_enable()
854 WREG32(mmVM_L2_CNTL2, tmp); in gmc_v8_0_gart_enable()
861 WREG32(mmVM_L2_CNTL3, tmp); in gmc_v8_0_gart_enable()
876 WREG32(mmVM_L2_CNTL4, tmp); in gmc_v8_0_gart_enable()
878 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); in gmc_v8_0_gart_enable()
879 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); in gmc_v8_0_gart_enable()
880 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); in gmc_v8_0_gart_enable()
881 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in gmc_v8_0_gart_enable()
883 WREG32(mmVM_CONTEXT0_CNTL2, 0); in gmc_v8_0_gart_enable()
888 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_gart_enable()
890 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); in gmc_v8_0_gart_enable()
891 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); in gmc_v8_0_gart_enable()
892 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); in gmc_v8_0_gart_enable()
899 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); in gmc_v8_0_gart_enable()
900 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v8_0_gart_enable()
903 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, in gmc_v8_0_gart_enable()
906 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, in gmc_v8_0_gart_enable()
911 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, in gmc_v8_0_gart_enable()
913 WREG32(mmVM_CONTEXT1_CNTL2, 4); in gmc_v8_0_gart_enable()
926 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_gart_enable()
968 WREG32(mmVM_CONTEXT0_CNTL, 0); in gmc_v8_0_gart_disable()
969 WREG32(mmVM_CONTEXT1_CNTL, 0); in gmc_v8_0_gart_disable()
975 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v8_0_gart_disable()
979 WREG32(mmVM_L2_CNTL, tmp); in gmc_v8_0_gart_disable()
980 WREG32(mmVM_L2_CNTL2, 0); in gmc_v8_0_gart_disable()
1354 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v8_0_soft_reset()
1360 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v8_0_soft_reset()
1400 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1404 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1410 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1414 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1499 WREG32(mmMC_HUB_MISC_HUB_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1503 WREG32(mmMC_HUB_MISC_SIP_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1507 WREG32(mmMC_HUB_MISC_VM_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1511 WREG32(mmMC_XPB_CLK_GAT, data); in fiji_update_mc_medium_grain_clock_gating()
1515 WREG32(mmATC_MISC_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1519 WREG32(mmMC_CITF_MISC_WR_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1523 WREG32(mmMC_CITF_MISC_RD_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1527 WREG32(mmMC_CITF_MISC_VM_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1531 WREG32(mmVM_L2_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1535 WREG32(mmMC_HUB_MISC_HUB_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1539 WREG32(mmMC_HUB_MISC_SIP_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1543 WREG32(mmMC_HUB_MISC_VM_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1547 WREG32(mmMC_XPB_CLK_GAT, data); in fiji_update_mc_medium_grain_clock_gating()
1551 WREG32(mmATC_MISC_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1555 WREG32(mmMC_CITF_MISC_WR_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1559 WREG32(mmMC_CITF_MISC_RD_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1563 WREG32(mmMC_CITF_MISC_VM_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1567 WREG32(mmVM_L2_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1579 WREG32(mmMC_HUB_MISC_HUB_CG, data); in fiji_update_mc_light_sleep()
1583 WREG32(mmMC_HUB_MISC_SIP_CG, data); in fiji_update_mc_light_sleep()
1587 WREG32(mmMC_HUB_MISC_VM_CG, data); in fiji_update_mc_light_sleep()
1591 WREG32(mmMC_XPB_CLK_GAT, data); in fiji_update_mc_light_sleep()
1595 WREG32(mmATC_MISC_CG, data); in fiji_update_mc_light_sleep()
1599 WREG32(mmMC_CITF_MISC_WR_CG, data); in fiji_update_mc_light_sleep()
1603 WREG32(mmMC_CITF_MISC_RD_CG, data); in fiji_update_mc_light_sleep()
1607 WREG32(mmMC_CITF_MISC_VM_CG, data); in fiji_update_mc_light_sleep()
1611 WREG32(mmVM_L2_CG, data); in fiji_update_mc_light_sleep()
1615 WREG32(mmMC_HUB_MISC_HUB_CG, data); in fiji_update_mc_light_sleep()
1619 WREG32(mmMC_HUB_MISC_SIP_CG, data); in fiji_update_mc_light_sleep()
1623 WREG32(mmMC_HUB_MISC_VM_CG, data); in fiji_update_mc_light_sleep()
1627 WREG32(mmMC_XPB_CLK_GAT, data); in fiji_update_mc_light_sleep()
1631 WREG32(mmATC_MISC_CG, data); in fiji_update_mc_light_sleep()
1635 WREG32(mmMC_CITF_MISC_WR_CG, data); in fiji_update_mc_light_sleep()
1639 WREG32(mmMC_CITF_MISC_RD_CG, data); in fiji_update_mc_light_sleep()
1643 WREG32(mmMC_CITF_MISC_VM_CG, data); in fiji_update_mc_light_sleep()
1647 WREG32(mmVM_L2_CG, data); in fiji_update_mc_light_sleep()