73 		WREG32(mmBIF_FB_EN, 0);  in gmc_v6_0_mc_stop()
77 		WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);  in gmc_v6_0_mc_stop()
91 	WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);  in gmc_v6_0_mc_resume()
95 	WREG32(mmBIF_FB_EN, tmp);  in gmc_v6_0_mc_resume()
173 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v6_0_mc_load_microcode()
174 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);  in gmc_v6_0_mc_load_microcode()
178 			WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));  in gmc_v6_0_mc_load_microcode()
179 			WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));  in gmc_v6_0_mc_load_microcode()
183 			WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));  in gmc_v6_0_mc_load_microcode()
186 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v6_0_mc_load_microcode()
187 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);  in gmc_v6_0_mc_load_microcode()
188 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);  in gmc_v6_0_mc_load_microcode()
224 		WREG32((0xb05 + j), 0x00000000);  in gmc_v6_0_mc_program()
225 		WREG32((0xb06 + j), 0x00000000);  in gmc_v6_0_mc_program()
226 		WREG32((0xb07 + j), 0x00000000);  in gmc_v6_0_mc_program()
227 		WREG32((0xb08 + j), 0x00000000);  in gmc_v6_0_mc_program()
228 		WREG32((0xb09 + j), 0x00000000);  in gmc_v6_0_mc_program()
230 	WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);  in gmc_v6_0_mc_program()
241 		WREG32(mmVGA_HDP_CONTROL, tmp);  in gmc_v6_0_mc_program()
246 		WREG32(mmVGA_RENDER_CONTROL, tmp);  in gmc_v6_0_mc_program()
249 	WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,  in gmc_v6_0_mc_program()
251 	WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,  in gmc_v6_0_mc_program()
253 	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,  in gmc_v6_0_mc_program()
255 	WREG32(mmMC_VM_AGP_BASE, 0);  in gmc_v6_0_mc_program()
256 	WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);  in gmc_v6_0_mc_program()
257 	WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);  in gmc_v6_0_mc_program()
350 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);  in gmc_v6_0_flush_gpu_tlb()
403 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v6_0_set_fault_enable_default()
434 	WREG32(mmVM_PRT_CNTL, tmp);  in gmc_v6_0_set_prt()
441 		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);  in gmc_v6_0_set_prt()
442 		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);  in gmc_v6_0_set_prt()
443 		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);  in gmc_v6_0_set_prt()
444 		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);  in gmc_v6_0_set_prt()
445 		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);  in gmc_v6_0_set_prt()
446 		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);  in gmc_v6_0_set_prt()
447 		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);  in gmc_v6_0_set_prt()
448 		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);  in gmc_v6_0_set_prt()
450 		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);  in gmc_v6_0_set_prt()
451 		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);  in gmc_v6_0_set_prt()
452 		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);  in gmc_v6_0_set_prt()
453 		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);  in gmc_v6_0_set_prt()
454 		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);  in gmc_v6_0_set_prt()
455 		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);  in gmc_v6_0_set_prt()
456 		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);  in gmc_v6_0_set_prt()
457 		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);  in gmc_v6_0_set_prt()
476 	WREG32(mmMC_VM_MX_L1_TLB_CNTL,  in gmc_v6_0_gart_enable()
484 	WREG32(mmVM_L2_CNTL,  in gmc_v6_0_gart_enable()
491 	WREG32(mmVM_L2_CNTL2,  in gmc_v6_0_gart_enable()
496 	WREG32(mmVM_L2_CNTL3,  in gmc_v6_0_gart_enable()
501 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);  in gmc_v6_0_gart_enable()
502 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);  in gmc_v6_0_gart_enable()
503 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);  in gmc_v6_0_gart_enable()
504 	WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,  in gmc_v6_0_gart_enable()
506 	WREG32(mmVM_CONTEXT0_CNTL2, 0);  in gmc_v6_0_gart_enable()
507 	WREG32(mmVM_CONTEXT0_CNTL,  in gmc_v6_0_gart_enable()
512 	WREG32(0x575, 0);  in gmc_v6_0_gart_enable()
513 	WREG32(0x576, 0);  in gmc_v6_0_gart_enable()
514 	WREG32(0x577, 0);  in gmc_v6_0_gart_enable()
518 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);  in gmc_v6_0_gart_enable()
519 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);  in gmc_v6_0_gart_enable()
526 			WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,  in gmc_v6_0_gart_enable()
529 			WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,  in gmc_v6_0_gart_enable()
534 	WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,  in gmc_v6_0_gart_enable()
536 	WREG32(mmVM_CONTEXT1_CNTL2, 4);  in gmc_v6_0_gart_enable()
537 	WREG32(mmVM_CONTEXT1_CNTL,  in gmc_v6_0_gart_enable()
584 	WREG32(mmVM_CONTEXT0_CNTL, 0);  in gmc_v6_0_gart_disable()
585 	WREG32(mmVM_CONTEXT1_CNTL, 0);  in gmc_v6_0_gart_disable()
587 	WREG32(mmMC_VM_MX_L1_TLB_CNTL,  in gmc_v6_0_gart_disable()
591 	WREG32(mmVM_L2_CNTL,  in gmc_v6_0_gart_disable()
596 	WREG32(mmVM_L2_CNTL2, 0);  in gmc_v6_0_gart_disable()
597 	WREG32(mmVM_L2_CNTL3,  in gmc_v6_0_gart_disable()
1005 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v6_0_soft_reset()
1011 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v6_0_soft_reset()
1040 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v6_0_vm_fault_interrupt_state()
1043 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v6_0_vm_fault_interrupt_state()
1048 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v6_0_vm_fault_interrupt_state()
1051 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v6_0_vm_fault_interrupt_state()