Lines Matching refs:vmid

131 			entry->src_id, entry->ring_id, entry->vmid,  in gmc_v11_0_process_interrupt()
180 uint8_t vmid, uint16_t *p_pasid) in gmc_v11_0_get_vmid_pasid_mapping_info() argument
182 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; in gmc_v11_0_get_vmid_pasid_mapping_info()
194 static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, in gmc_v11_0_flush_vm_hub() argument
199 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); in gmc_v11_0_flush_vm_hub()
238 tmp &= 1 << vmid; in gmc_v11_0_flush_vm_hub()
285 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, in gmc_v11_0_flush_gpu_tlb() argument
301 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); in gmc_v11_0_flush_gpu_tlb()
306 1 << vmid); in gmc_v11_0_flush_gpu_tlb()
311 gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0); in gmc_v11_0_flush_gpu_tlb()
330 int vmid, i; in gmc_v11_0_flush_gpu_tlb_pasid() local
362 for (vmid = 1; vmid < 16; vmid++) { in gmc_v11_0_flush_gpu_tlb_pasid()
364 ret = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid, in gmc_v11_0_flush_gpu_tlb_pasid()
369 gmc_v11_0_flush_gpu_tlb(adev, vmid, in gmc_v11_0_flush_gpu_tlb_pasid()
372 gmc_v11_0_flush_gpu_tlb(adev, vmid, in gmc_v11_0_flush_gpu_tlb_pasid()
382 unsigned int vmid, uint64_t pd_addr) in gmc_v11_0_emit_flush_gpu_tlb() argument
386 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); in gmc_v11_0_emit_flush_gpu_tlb()
404 (hub->ctx_addr_distance * vmid), in gmc_v11_0_emit_flush_gpu_tlb()
408 (hub->ctx_addr_distance * vmid), in gmc_v11_0_emit_flush_gpu_tlb()
415 req, 1 << vmid); in gmc_v11_0_emit_flush_gpu_tlb()
429 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, in gmc_v11_0_emit_pasid_mapping() argument
440 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; in gmc_v11_0_emit_pasid_mapping()
442 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; in gmc_v11_0_emit_pasid_mapping()