Lines Matching refs:gfx_v9_4_3_xcc_select_se_sh
523 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num,
669 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh,
1125 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff,
1133 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff,
1143 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3777 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
3800 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3824 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
3839 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3854 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id);
3872 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3955 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx,
3973 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
4003 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id);
4010 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
4024 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx,
4031 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
4065 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id);
4068 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
4320 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id);
4352 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,