722 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
734 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
957 						(const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));  in gfx_v9_0_init_golden_registers()
1409 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)  in gfx_v9_0_get_csb_size()
1411 	u32 count = 0;  in gfx_v9_0_get_csb_size()
1438 				    volatile u32 *buffer)  in gfx_v9_0_get_csb_buffer()
1440 	u32 count = 0, i;  in gfx_v9_0_get_csb_buffer()
1684 	u32 *hpd;  in gfx_v9_0_mec_init()
1687 	u32 *fw;  in gfx_v9_0_mec_init()
1808 				  u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)  in gfx_v9_0_select_me_pipe_q()
1836 	u32 gb_addr_config;  in gfx_v9_0_gpu_early_init()
2219 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,  in gfx_v9_0_select_se_sh()
2220 			   u32 instance, int xcc_id)  in gfx_v9_0_select_se_sh()
2222 	u32 data;  in gfx_v9_0_select_se_sh()
2242 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)  in gfx_v9_0_get_rb_active_bitmap()
2244 	u32 data, mask;  in gfx_v9_0_get_rb_active_bitmap()
2261 	u32 data;  in gfx_v9_0_setup_rb()
2262 	u32 active_rbs = 0;  in gfx_v9_0_setup_rb()
2263 	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /  in gfx_v9_0_setup_rb()
2380 	u32 tmp;  in gfx_v9_0_constants_init()
2429 	u32 i, j, k;  in gfx_v9_0_wait_for_rlc_serdes()
2430 	u32 mask;  in gfx_v9_0_wait_for_rlc_serdes()
2468 	u32 tmp;  in gfx_v9_0_enable_gui_idle_interrupt()
2542 	u32 tmp = 0;  in gfx_v9_1_init_rlc_save_restore_list()
2544 	u32 *register_list_format =  in gfx_v9_1_init_rlc_save_restore_list()
2851 	u32 rlc_ucode_ver;  in gfx_v9_0_rlc_start()
2957 	u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);  in gfx_v9_0_cp_gfx_enable()
3096 	u32 tmp;  in gfx_v9_0_cp_gfx_resume()
3097 	u32 rb_bufsz;  in gfx_v9_0_cp_gfx_resume()
3179 	u32 tmp;  in gfx_v9_0_cp_compute_load_microcode()
3722 	u32 tmp;  in gfx_v9_0_init_tcp_config()
3858 	u32 grbm_soft_reset = 0;  in gfx_v9_0_soft_reset()
3859 	u32 tmp;  in gfx_v9_0_soft_reset()
4059 static const u32 vgpr_init_compute_shader[] =
4082 static const u32 sgpr_init_compute_shader[] =
4093 static const u32 vgpr_init_compute_shader_arcturus[] = {
4357 	const u32 *vgpr_init_shader_ptr;  in gfx_v9_0_do_edc_gpr_workarounds()
4400 	for (i = 0; i < vgpr_init_shader_size/sizeof(u32); i++)  in gfx_v9_0_do_edc_gpr_workarounds()
4885 	u32 reg, data;  in gfx_v9_0_update_spm_vmid_internal()
4933 static bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)  in gfx_v9_0_is_rlcg_access_range()
5109 	u32 ref_and_mask, reg_mem_engine;  in gfx_v9_0_ring_emit_hdp_flush()
5141 	u32 header, control = 0;  in gfx_v9_0_ring_emit_ib_gfx()
5179 	u32 control = ring->ring[offset];  in gfx_v9_0_ring_patch_cntl()
5258 	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);  in gfx_v9_0_ring_emit_ib_compute()
5730 	u32 mec_int_cntl, mec_int_cntl_reg;  in gfx_v9_0_set_compute_eop_interrupt_state()
7170 						 u32 bitmap)  in gfx_v9_0_set_user_cu_inactive_bitmap()
7172 	u32 data;  in gfx_v9_0_set_user_cu_inactive_bitmap()
7183 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)  in gfx_v9_0_get_cu_active_bitmap()
7185 	u32 data, mask;  in gfx_v9_0_get_cu_active_bitmap()
7202 	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;  in gfx_v9_0_get_cu_info()