Lines Matching +full:0 +full:x8c20
53 #define NUM_SIMD_PER_CU 0x4 /* missing from the gfx_7 IP headers */
113 (0x0e00 << 16) | (0xc12c >> 2),
114 0x00000000,
115 (0x0e00 << 16) | (0xc140 >> 2),
116 0x00000000,
117 (0x0e00 << 16) | (0xc150 >> 2),
118 0x00000000,
119 (0x0e00 << 16) | (0xc15c >> 2),
120 0x00000000,
121 (0x0e00 << 16) | (0xc168 >> 2),
122 0x00000000,
123 (0x0e00 << 16) | (0xc170 >> 2),
124 0x00000000,
125 (0x0e00 << 16) | (0xc178 >> 2),
126 0x00000000,
127 (0x0e00 << 16) | (0xc204 >> 2),
128 0x00000000,
129 (0x0e00 << 16) | (0xc2b4 >> 2),
130 0x00000000,
131 (0x0e00 << 16) | (0xc2b8 >> 2),
132 0x00000000,
133 (0x0e00 << 16) | (0xc2bc >> 2),
134 0x00000000,
135 (0x0e00 << 16) | (0xc2c0 >> 2),
136 0x00000000,
137 (0x0e00 << 16) | (0x8228 >> 2),
138 0x00000000,
139 (0x0e00 << 16) | (0x829c >> 2),
140 0x00000000,
141 (0x0e00 << 16) | (0x869c >> 2),
142 0x00000000,
143 (0x0600 << 16) | (0x98f4 >> 2),
144 0x00000000,
145 (0x0e00 << 16) | (0x98f8 >> 2),
146 0x00000000,
147 (0x0e00 << 16) | (0x9900 >> 2),
148 0x00000000,
149 (0x0e00 << 16) | (0xc260 >> 2),
150 0x00000000,
151 (0x0e00 << 16) | (0x90e8 >> 2),
152 0x00000000,
153 (0x0e00 << 16) | (0x3c000 >> 2),
154 0x00000000,
155 (0x0e00 << 16) | (0x3c00c >> 2),
156 0x00000000,
157 (0x0e00 << 16) | (0x8c1c >> 2),
158 0x00000000,
159 (0x0e00 << 16) | (0x9700 >> 2),
160 0x00000000,
161 (0x0e00 << 16) | (0xcd20 >> 2),
162 0x00000000,
163 (0x4e00 << 16) | (0xcd20 >> 2),
164 0x00000000,
165 (0x5e00 << 16) | (0xcd20 >> 2),
166 0x00000000,
167 (0x6e00 << 16) | (0xcd20 >> 2),
168 0x00000000,
169 (0x7e00 << 16) | (0xcd20 >> 2),
170 0x00000000,
171 (0x8e00 << 16) | (0xcd20 >> 2),
172 0x00000000,
173 (0x9e00 << 16) | (0xcd20 >> 2),
174 0x00000000,
175 (0xae00 << 16) | (0xcd20 >> 2),
176 0x00000000,
177 (0xbe00 << 16) | (0xcd20 >> 2),
178 0x00000000,
179 (0x0e00 << 16) | (0x89bc >> 2),
180 0x00000000,
181 (0x0e00 << 16) | (0x8900 >> 2),
182 0x00000000,
183 0x3,
184 (0x0e00 << 16) | (0xc130 >> 2),
185 0x00000000,
186 (0x0e00 << 16) | (0xc134 >> 2),
187 0x00000000,
188 (0x0e00 << 16) | (0xc1fc >> 2),
189 0x00000000,
190 (0x0e00 << 16) | (0xc208 >> 2),
191 0x00000000,
192 (0x0e00 << 16) | (0xc264 >> 2),
193 0x00000000,
194 (0x0e00 << 16) | (0xc268 >> 2),
195 0x00000000,
196 (0x0e00 << 16) | (0xc26c >> 2),
197 0x00000000,
198 (0x0e00 << 16) | (0xc270 >> 2),
199 0x00000000,
200 (0x0e00 << 16) | (0xc274 >> 2),
201 0x00000000,
202 (0x0e00 << 16) | (0xc278 >> 2),
203 0x00000000,
204 (0x0e00 << 16) | (0xc27c >> 2),
205 0x00000000,
206 (0x0e00 << 16) | (0xc280 >> 2),
207 0x00000000,
208 (0x0e00 << 16) | (0xc284 >> 2),
209 0x00000000,
210 (0x0e00 << 16) | (0xc288 >> 2),
211 0x00000000,
212 (0x0e00 << 16) | (0xc28c >> 2),
213 0x00000000,
214 (0x0e00 << 16) | (0xc290 >> 2),
215 0x00000000,
216 (0x0e00 << 16) | (0xc294 >> 2),
217 0x00000000,
218 (0x0e00 << 16) | (0xc298 >> 2),
219 0x00000000,
220 (0x0e00 << 16) | (0xc29c >> 2),
221 0x00000000,
222 (0x0e00 << 16) | (0xc2a0 >> 2),
223 0x00000000,
224 (0x0e00 << 16) | (0xc2a4 >> 2),
225 0x00000000,
226 (0x0e00 << 16) | (0xc2a8 >> 2),
227 0x00000000,
228 (0x0e00 << 16) | (0xc2ac >> 2),
229 0x00000000,
230 (0x0e00 << 16) | (0xc2b0 >> 2),
231 0x00000000,
232 (0x0e00 << 16) | (0x301d0 >> 2),
233 0x00000000,
234 (0x0e00 << 16) | (0x30238 >> 2),
235 0x00000000,
236 (0x0e00 << 16) | (0x30250 >> 2),
237 0x00000000,
238 (0x0e00 << 16) | (0x30254 >> 2),
239 0x00000000,
240 (0x0e00 << 16) | (0x30258 >> 2),
241 0x00000000,
242 (0x0e00 << 16) | (0x3025c >> 2),
243 0x00000000,
244 (0x4e00 << 16) | (0xc900 >> 2),
245 0x00000000,
246 (0x5e00 << 16) | (0xc900 >> 2),
247 0x00000000,
248 (0x6e00 << 16) | (0xc900 >> 2),
249 0x00000000,
250 (0x7e00 << 16) | (0xc900 >> 2),
251 0x00000000,
252 (0x8e00 << 16) | (0xc900 >> 2),
253 0x00000000,
254 (0x9e00 << 16) | (0xc900 >> 2),
255 0x00000000,
256 (0xae00 << 16) | (0xc900 >> 2),
257 0x00000000,
258 (0xbe00 << 16) | (0xc900 >> 2),
259 0x00000000,
260 (0x4e00 << 16) | (0xc904 >> 2),
261 0x00000000,
262 (0x5e00 << 16) | (0xc904 >> 2),
263 0x00000000,
264 (0x6e00 << 16) | (0xc904 >> 2),
265 0x00000000,
266 (0x7e00 << 16) | (0xc904 >> 2),
267 0x00000000,
268 (0x8e00 << 16) | (0xc904 >> 2),
269 0x00000000,
270 (0x9e00 << 16) | (0xc904 >> 2),
271 0x00000000,
272 (0xae00 << 16) | (0xc904 >> 2),
273 0x00000000,
274 (0xbe00 << 16) | (0xc904 >> 2),
275 0x00000000,
276 (0x4e00 << 16) | (0xc908 >> 2),
277 0x00000000,
278 (0x5e00 << 16) | (0xc908 >> 2),
279 0x00000000,
280 (0x6e00 << 16) | (0xc908 >> 2),
281 0x00000000,
282 (0x7e00 << 16) | (0xc908 >> 2),
283 0x00000000,
284 (0x8e00 << 16) | (0xc908 >> 2),
285 0x00000000,
286 (0x9e00 << 16) | (0xc908 >> 2),
287 0x00000000,
288 (0xae00 << 16) | (0xc908 >> 2),
289 0x00000000,
290 (0xbe00 << 16) | (0xc908 >> 2),
291 0x00000000,
292 (0x4e00 << 16) | (0xc90c >> 2),
293 0x00000000,
294 (0x5e00 << 16) | (0xc90c >> 2),
295 0x00000000,
296 (0x6e00 << 16) | (0xc90c >> 2),
297 0x00000000,
298 (0x7e00 << 16) | (0xc90c >> 2),
299 0x00000000,
300 (0x8e00 << 16) | (0xc90c >> 2),
301 0x00000000,
302 (0x9e00 << 16) | (0xc90c >> 2),
303 0x00000000,
304 (0xae00 << 16) | (0xc90c >> 2),
305 0x00000000,
306 (0xbe00 << 16) | (0xc90c >> 2),
307 0x00000000,
308 (0x4e00 << 16) | (0xc910 >> 2),
309 0x00000000,
310 (0x5e00 << 16) | (0xc910 >> 2),
311 0x00000000,
312 (0x6e00 << 16) | (0xc910 >> 2),
313 0x00000000,
314 (0x7e00 << 16) | (0xc910 >> 2),
315 0x00000000,
316 (0x8e00 << 16) | (0xc910 >> 2),
317 0x00000000,
318 (0x9e00 << 16) | (0xc910 >> 2),
319 0x00000000,
320 (0xae00 << 16) | (0xc910 >> 2),
321 0x00000000,
322 (0xbe00 << 16) | (0xc910 >> 2),
323 0x00000000,
324 (0x0e00 << 16) | (0xc99c >> 2),
325 0x00000000,
326 (0x0e00 << 16) | (0x9834 >> 2),
327 0x00000000,
328 (0x0000 << 16) | (0x30f00 >> 2),
329 0x00000000,
330 (0x0001 << 16) | (0x30f00 >> 2),
331 0x00000000,
332 (0x0000 << 16) | (0x30f04 >> 2),
333 0x00000000,
334 (0x0001 << 16) | (0x30f04 >> 2),
335 0x00000000,
336 (0x0000 << 16) | (0x30f08 >> 2),
337 0x00000000,
338 (0x0001 << 16) | (0x30f08 >> 2),
339 0x00000000,
340 (0x0000 << 16) | (0x30f0c >> 2),
341 0x00000000,
342 (0x0001 << 16) | (0x30f0c >> 2),
343 0x00000000,
344 (0x0600 << 16) | (0x9b7c >> 2),
345 0x00000000,
346 (0x0e00 << 16) | (0x8a14 >> 2),
347 0x00000000,
348 (0x0e00 << 16) | (0x8a18 >> 2),
349 0x00000000,
350 (0x0600 << 16) | (0x30a00 >> 2),
351 0x00000000,
352 (0x0e00 << 16) | (0x8bf0 >> 2),
353 0x00000000,
354 (0x0e00 << 16) | (0x8bcc >> 2),
355 0x00000000,
356 (0x0e00 << 16) | (0x8b24 >> 2),
357 0x00000000,
358 (0x0e00 << 16) | (0x30a04 >> 2),
359 0x00000000,
360 (0x0600 << 16) | (0x30a10 >> 2),
361 0x00000000,
362 (0x0600 << 16) | (0x30a14 >> 2),
363 0x00000000,
364 (0x0600 << 16) | (0x30a18 >> 2),
365 0x00000000,
366 (0x0600 << 16) | (0x30a2c >> 2),
367 0x00000000,
368 (0x0e00 << 16) | (0xc700 >> 2),
369 0x00000000,
370 (0x0e00 << 16) | (0xc704 >> 2),
371 0x00000000,
372 (0x0e00 << 16) | (0xc708 >> 2),
373 0x00000000,
374 (0x0e00 << 16) | (0xc768 >> 2),
375 0x00000000,
376 (0x0400 << 16) | (0xc770 >> 2),
377 0x00000000,
378 (0x0400 << 16) | (0xc774 >> 2),
379 0x00000000,
380 (0x0400 << 16) | (0xc778 >> 2),
381 0x00000000,
382 (0x0400 << 16) | (0xc77c >> 2),
383 0x00000000,
384 (0x0400 << 16) | (0xc780 >> 2),
385 0x00000000,
386 (0x0400 << 16) | (0xc784 >> 2),
387 0x00000000,
388 (0x0400 << 16) | (0xc788 >> 2),
389 0x00000000,
390 (0x0400 << 16) | (0xc78c >> 2),
391 0x00000000,
392 (0x0400 << 16) | (0xc798 >> 2),
393 0x00000000,
394 (0x0400 << 16) | (0xc79c >> 2),
395 0x00000000,
396 (0x0400 << 16) | (0xc7a0 >> 2),
397 0x00000000,
398 (0x0400 << 16) | (0xc7a4 >> 2),
399 0x00000000,
400 (0x0400 << 16) | (0xc7a8 >> 2),
401 0x00000000,
402 (0x0400 << 16) | (0xc7ac >> 2),
403 0x00000000,
404 (0x0400 << 16) | (0xc7b0 >> 2),
405 0x00000000,
406 (0x0400 << 16) | (0xc7b4 >> 2),
407 0x00000000,
408 (0x0e00 << 16) | (0x9100 >> 2),
409 0x00000000,
410 (0x0e00 << 16) | (0x3c010 >> 2),
411 0x00000000,
412 (0x0e00 << 16) | (0x92a8 >> 2),
413 0x00000000,
414 (0x0e00 << 16) | (0x92ac >> 2),
415 0x00000000,
416 (0x0e00 << 16) | (0x92b4 >> 2),
417 0x00000000,
418 (0x0e00 << 16) | (0x92b8 >> 2),
419 0x00000000,
420 (0x0e00 << 16) | (0x92bc >> 2),
421 0x00000000,
422 (0x0e00 << 16) | (0x92c0 >> 2),
423 0x00000000,
424 (0x0e00 << 16) | (0x92c4 >> 2),
425 0x00000000,
426 (0x0e00 << 16) | (0x92c8 >> 2),
427 0x00000000,
428 (0x0e00 << 16) | (0x92cc >> 2),
429 0x00000000,
430 (0x0e00 << 16) | (0x92d0 >> 2),
431 0x00000000,
432 (0x0e00 << 16) | (0x8c00 >> 2),
433 0x00000000,
434 (0x0e00 << 16) | (0x8c04 >> 2),
435 0x00000000,
436 (0x0e00 << 16) | (0x8c20 >> 2),
437 0x00000000,
438 (0x0e00 << 16) | (0x8c38 >> 2),
439 0x00000000,
440 (0x0e00 << 16) | (0x8c3c >> 2),
441 0x00000000,
442 (0x0e00 << 16) | (0xae00 >> 2),
443 0x00000000,
444 (0x0e00 << 16) | (0x9604 >> 2),
445 0x00000000,
446 (0x0e00 << 16) | (0xac08 >> 2),
447 0x00000000,
448 (0x0e00 << 16) | (0xac0c >> 2),
449 0x00000000,
450 (0x0e00 << 16) | (0xac10 >> 2),
451 0x00000000,
452 (0x0e00 << 16) | (0xac14 >> 2),
453 0x00000000,
454 (0x0e00 << 16) | (0xac58 >> 2),
455 0x00000000,
456 (0x0e00 << 16) | (0xac68 >> 2),
457 0x00000000,
458 (0x0e00 << 16) | (0xac6c >> 2),
459 0x00000000,
460 (0x0e00 << 16) | (0xac70 >> 2),
461 0x00000000,
462 (0x0e00 << 16) | (0xac74 >> 2),
463 0x00000000,
464 (0x0e00 << 16) | (0xac78 >> 2),
465 0x00000000,
466 (0x0e00 << 16) | (0xac7c >> 2),
467 0x00000000,
468 (0x0e00 << 16) | (0xac80 >> 2),
469 0x00000000,
470 (0x0e00 << 16) | (0xac84 >> 2),
471 0x00000000,
472 (0x0e00 << 16) | (0xac88 >> 2),
473 0x00000000,
474 (0x0e00 << 16) | (0xac8c >> 2),
475 0x00000000,
476 (0x0e00 << 16) | (0x970c >> 2),
477 0x00000000,
478 (0x0e00 << 16) | (0x9714 >> 2),
479 0x00000000,
480 (0x0e00 << 16) | (0x9718 >> 2),
481 0x00000000,
482 (0x0e00 << 16) | (0x971c >> 2),
483 0x00000000,
484 (0x0e00 << 16) | (0x31068 >> 2),
485 0x00000000,
486 (0x4e00 << 16) | (0x31068 >> 2),
487 0x00000000,
488 (0x5e00 << 16) | (0x31068 >> 2),
489 0x00000000,
490 (0x6e00 << 16) | (0x31068 >> 2),
491 0x00000000,
492 (0x7e00 << 16) | (0x31068 >> 2),
493 0x00000000,
494 (0x8e00 << 16) | (0x31068 >> 2),
495 0x00000000,
496 (0x9e00 << 16) | (0x31068 >> 2),
497 0x00000000,
498 (0xae00 << 16) | (0x31068 >> 2),
499 0x00000000,
500 (0xbe00 << 16) | (0x31068 >> 2),
501 0x00000000,
502 (0x0e00 << 16) | (0xcd10 >> 2),
503 0x00000000,
504 (0x0e00 << 16) | (0xcd14 >> 2),
505 0x00000000,
506 (0x0e00 << 16) | (0x88b0 >> 2),
507 0x00000000,
508 (0x0e00 << 16) | (0x88b4 >> 2),
509 0x00000000,
510 (0x0e00 << 16) | (0x88b8 >> 2),
511 0x00000000,
512 (0x0e00 << 16) | (0x88bc >> 2),
513 0x00000000,
514 (0x0400 << 16) | (0x89c0 >> 2),
515 0x00000000,
516 (0x0e00 << 16) | (0x88c4 >> 2),
517 0x00000000,
518 (0x0e00 << 16) | (0x88c8 >> 2),
519 0x00000000,
520 (0x0e00 << 16) | (0x88d0 >> 2),
521 0x00000000,
522 (0x0e00 << 16) | (0x88d4 >> 2),
523 0x00000000,
524 (0x0e00 << 16) | (0x88d8 >> 2),
525 0x00000000,
526 (0x0e00 << 16) | (0x8980 >> 2),
527 0x00000000,
528 (0x0e00 << 16) | (0x30938 >> 2),
529 0x00000000,
530 (0x0e00 << 16) | (0x3093c >> 2),
531 0x00000000,
532 (0x0e00 << 16) | (0x30940 >> 2),
533 0x00000000,
534 (0x0e00 << 16) | (0x89a0 >> 2),
535 0x00000000,
536 (0x0e00 << 16) | (0x30900 >> 2),
537 0x00000000,
538 (0x0e00 << 16) | (0x30904 >> 2),
539 0x00000000,
540 (0x0e00 << 16) | (0x89b4 >> 2),
541 0x00000000,
542 (0x0e00 << 16) | (0x3c210 >> 2),
543 0x00000000,
544 (0x0e00 << 16) | (0x3c214 >> 2),
545 0x00000000,
546 (0x0e00 << 16) | (0x3c218 >> 2),
547 0x00000000,
548 (0x0e00 << 16) | (0x8904 >> 2),
549 0x00000000,
550 0x5,
551 (0x0e00 << 16) | (0x8c28 >> 2),
552 (0x0e00 << 16) | (0x8c2c >> 2),
553 (0x0e00 << 16) | (0x8c30 >> 2),
554 (0x0e00 << 16) | (0x8c34 >> 2),
555 (0x0e00 << 16) | (0x9600 >> 2),
559 (0x0e00 << 16) | (0xc12c >> 2),
560 0x00000000,
561 (0x0e00 << 16) | (0xc140 >> 2),
562 0x00000000,
563 (0x0e00 << 16) | (0xc150 >> 2),
564 0x00000000,
565 (0x0e00 << 16) | (0xc15c >> 2),
566 0x00000000,
567 (0x0e00 << 16) | (0xc168 >> 2),
568 0x00000000,
569 (0x0e00 << 16) | (0xc170 >> 2),
570 0x00000000,
571 (0x0e00 << 16) | (0xc204 >> 2),
572 0x00000000,
573 (0x0e00 << 16) | (0xc2b4 >> 2),
574 0x00000000,
575 (0x0e00 << 16) | (0xc2b8 >> 2),
576 0x00000000,
577 (0x0e00 << 16) | (0xc2bc >> 2),
578 0x00000000,
579 (0x0e00 << 16) | (0xc2c0 >> 2),
580 0x00000000,
581 (0x0e00 << 16) | (0x8228 >> 2),
582 0x00000000,
583 (0x0e00 << 16) | (0x829c >> 2),
584 0x00000000,
585 (0x0e00 << 16) | (0x869c >> 2),
586 0x00000000,
587 (0x0600 << 16) | (0x98f4 >> 2),
588 0x00000000,
589 (0x0e00 << 16) | (0x98f8 >> 2),
590 0x00000000,
591 (0x0e00 << 16) | (0x9900 >> 2),
592 0x00000000,
593 (0x0e00 << 16) | (0xc260 >> 2),
594 0x00000000,
595 (0x0e00 << 16) | (0x90e8 >> 2),
596 0x00000000,
597 (0x0e00 << 16) | (0x3c000 >> 2),
598 0x00000000,
599 (0x0e00 << 16) | (0x3c00c >> 2),
600 0x00000000,
601 (0x0e00 << 16) | (0x8c1c >> 2),
602 0x00000000,
603 (0x0e00 << 16) | (0x9700 >> 2),
604 0x00000000,
605 (0x0e00 << 16) | (0xcd20 >> 2),
606 0x00000000,
607 (0x4e00 << 16) | (0xcd20 >> 2),
608 0x00000000,
609 (0x5e00 << 16) | (0xcd20 >> 2),
610 0x00000000,
611 (0x6e00 << 16) | (0xcd20 >> 2),
612 0x00000000,
613 (0x7e00 << 16) | (0xcd20 >> 2),
614 0x00000000,
615 (0x0e00 << 16) | (0x89bc >> 2),
616 0x00000000,
617 (0x0e00 << 16) | (0x8900 >> 2),
618 0x00000000,
619 0x3,
620 (0x0e00 << 16) | (0xc130 >> 2),
621 0x00000000,
622 (0x0e00 << 16) | (0xc134 >> 2),
623 0x00000000,
624 (0x0e00 << 16) | (0xc1fc >> 2),
625 0x00000000,
626 (0x0e00 << 16) | (0xc208 >> 2),
627 0x00000000,
628 (0x0e00 << 16) | (0xc264 >> 2),
629 0x00000000,
630 (0x0e00 << 16) | (0xc268 >> 2),
631 0x00000000,
632 (0x0e00 << 16) | (0xc26c >> 2),
633 0x00000000,
634 (0x0e00 << 16) | (0xc270 >> 2),
635 0x00000000,
636 (0x0e00 << 16) | (0xc274 >> 2),
637 0x00000000,
638 (0x0e00 << 16) | (0xc28c >> 2),
639 0x00000000,
640 (0x0e00 << 16) | (0xc290 >> 2),
641 0x00000000,
642 (0x0e00 << 16) | (0xc294 >> 2),
643 0x00000000,
644 (0x0e00 << 16) | (0xc298 >> 2),
645 0x00000000,
646 (0x0e00 << 16) | (0xc2a0 >> 2),
647 0x00000000,
648 (0x0e00 << 16) | (0xc2a4 >> 2),
649 0x00000000,
650 (0x0e00 << 16) | (0xc2a8 >> 2),
651 0x00000000,
652 (0x0e00 << 16) | (0xc2ac >> 2),
653 0x00000000,
654 (0x0e00 << 16) | (0x301d0 >> 2),
655 0x00000000,
656 (0x0e00 << 16) | (0x30238 >> 2),
657 0x00000000,
658 (0x0e00 << 16) | (0x30250 >> 2),
659 0x00000000,
660 (0x0e00 << 16) | (0x30254 >> 2),
661 0x00000000,
662 (0x0e00 << 16) | (0x30258 >> 2),
663 0x00000000,
664 (0x0e00 << 16) | (0x3025c >> 2),
665 0x00000000,
666 (0x4e00 << 16) | (0xc900 >> 2),
667 0x00000000,
668 (0x5e00 << 16) | (0xc900 >> 2),
669 0x00000000,
670 (0x6e00 << 16) | (0xc900 >> 2),
671 0x00000000,
672 (0x7e00 << 16) | (0xc900 >> 2),
673 0x00000000,
674 (0x4e00 << 16) | (0xc904 >> 2),
675 0x00000000,
676 (0x5e00 << 16) | (0xc904 >> 2),
677 0x00000000,
678 (0x6e00 << 16) | (0xc904 >> 2),
679 0x00000000,
680 (0x7e00 << 16) | (0xc904 >> 2),
681 0x00000000,
682 (0x4e00 << 16) | (0xc908 >> 2),
683 0x00000000,
684 (0x5e00 << 16) | (0xc908 >> 2),
685 0x00000000,
686 (0x6e00 << 16) | (0xc908 >> 2),
687 0x00000000,
688 (0x7e00 << 16) | (0xc908 >> 2),
689 0x00000000,
690 (0x4e00 << 16) | (0xc90c >> 2),
691 0x00000000,
692 (0x5e00 << 16) | (0xc90c >> 2),
693 0x00000000,
694 (0x6e00 << 16) | (0xc90c >> 2),
695 0x00000000,
696 (0x7e00 << 16) | (0xc90c >> 2),
697 0x00000000,
698 (0x4e00 << 16) | (0xc910 >> 2),
699 0x00000000,
700 (0x5e00 << 16) | (0xc910 >> 2),
701 0x00000000,
702 (0x6e00 << 16) | (0xc910 >> 2),
703 0x00000000,
704 (0x7e00 << 16) | (0xc910 >> 2),
705 0x00000000,
706 (0x0e00 << 16) | (0xc99c >> 2),
707 0x00000000,
708 (0x0e00 << 16) | (0x9834 >> 2),
709 0x00000000,
710 (0x0000 << 16) | (0x30f00 >> 2),
711 0x00000000,
712 (0x0000 << 16) | (0x30f04 >> 2),
713 0x00000000,
714 (0x0000 << 16) | (0x30f08 >> 2),
715 0x00000000,
716 (0x0000 << 16) | (0x30f0c >> 2),
717 0x00000000,
718 (0x0600 << 16) | (0x9b7c >> 2),
719 0x00000000,
720 (0x0e00 << 16) | (0x8a14 >> 2),
721 0x00000000,
722 (0x0e00 << 16) | (0x8a18 >> 2),
723 0x00000000,
724 (0x0600 << 16) | (0x30a00 >> 2),
725 0x00000000,
726 (0x0e00 << 16) | (0x8bf0 >> 2),
727 0x00000000,
728 (0x0e00 << 16) | (0x8bcc >> 2),
729 0x00000000,
730 (0x0e00 << 16) | (0x8b24 >> 2),
731 0x00000000,
732 (0x0e00 << 16) | (0x30a04 >> 2),
733 0x00000000,
734 (0x0600 << 16) | (0x30a10 >> 2),
735 0x00000000,
736 (0x0600 << 16) | (0x30a14 >> 2),
737 0x00000000,
738 (0x0600 << 16) | (0x30a18 >> 2),
739 0x00000000,
740 (0x0600 << 16) | (0x30a2c >> 2),
741 0x00000000,
742 (0x0e00 << 16) | (0xc700 >> 2),
743 0x00000000,
744 (0x0e00 << 16) | (0xc704 >> 2),
745 0x00000000,
746 (0x0e00 << 16) | (0xc708 >> 2),
747 0x00000000,
748 (0x0e00 << 16) | (0xc768 >> 2),
749 0x00000000,
750 (0x0400 << 16) | (0xc770 >> 2),
751 0x00000000,
752 (0x0400 << 16) | (0xc774 >> 2),
753 0x00000000,
754 (0x0400 << 16) | (0xc798 >> 2),
755 0x00000000,
756 (0x0400 << 16) | (0xc79c >> 2),
757 0x00000000,
758 (0x0e00 << 16) | (0x9100 >> 2),
759 0x00000000,
760 (0x0e00 << 16) | (0x3c010 >> 2),
761 0x00000000,
762 (0x0e00 << 16) | (0x8c00 >> 2),
763 0x00000000,
764 (0x0e00 << 16) | (0x8c04 >> 2),
765 0x00000000,
766 (0x0e00 << 16) | (0x8c20 >> 2),
767 0x00000000,
768 (0x0e00 << 16) | (0x8c38 >> 2),
769 0x00000000,
770 (0x0e00 << 16) | (0x8c3c >> 2),
771 0x00000000,
772 (0x0e00 << 16) | (0xae00 >> 2),
773 0x00000000,
774 (0x0e00 << 16) | (0x9604 >> 2),
775 0x00000000,
776 (0x0e00 << 16) | (0xac08 >> 2),
777 0x00000000,
778 (0x0e00 << 16) | (0xac0c >> 2),
779 0x00000000,
780 (0x0e00 << 16) | (0xac10 >> 2),
781 0x00000000,
782 (0x0e00 << 16) | (0xac14 >> 2),
783 0x00000000,
784 (0x0e00 << 16) | (0xac58 >> 2),
785 0x00000000,
786 (0x0e00 << 16) | (0xac68 >> 2),
787 0x00000000,
788 (0x0e00 << 16) | (0xac6c >> 2),
789 0x00000000,
790 (0x0e00 << 16) | (0xac70 >> 2),
791 0x00000000,
792 (0x0e00 << 16) | (0xac74 >> 2),
793 0x00000000,
794 (0x0e00 << 16) | (0xac78 >> 2),
795 0x00000000,
796 (0x0e00 << 16) | (0xac7c >> 2),
797 0x00000000,
798 (0x0e00 << 16) | (0xac80 >> 2),
799 0x00000000,
800 (0x0e00 << 16) | (0xac84 >> 2),
801 0x00000000,
802 (0x0e00 << 16) | (0xac88 >> 2),
803 0x00000000,
804 (0x0e00 << 16) | (0xac8c >> 2),
805 0x00000000,
806 (0x0e00 << 16) | (0x970c >> 2),
807 0x00000000,
808 (0x0e00 << 16) | (0x9714 >> 2),
809 0x00000000,
810 (0x0e00 << 16) | (0x9718 >> 2),
811 0x00000000,
812 (0x0e00 << 16) | (0x971c >> 2),
813 0x00000000,
814 (0x0e00 << 16) | (0x31068 >> 2),
815 0x00000000,
816 (0x4e00 << 16) | (0x31068 >> 2),
817 0x00000000,
818 (0x5e00 << 16) | (0x31068 >> 2),
819 0x00000000,
820 (0x6e00 << 16) | (0x31068 >> 2),
821 0x00000000,
822 (0x7e00 << 16) | (0x31068 >> 2),
823 0x00000000,
824 (0x0e00 << 16) | (0xcd10 >> 2),
825 0x00000000,
826 (0x0e00 << 16) | (0xcd14 >> 2),
827 0x00000000,
828 (0x0e00 << 16) | (0x88b0 >> 2),
829 0x00000000,
830 (0x0e00 << 16) | (0x88b4 >> 2),
831 0x00000000,
832 (0x0e00 << 16) | (0x88b8 >> 2),
833 0x00000000,
834 (0x0e00 << 16) | (0x88bc >> 2),
835 0x00000000,
836 (0x0400 << 16) | (0x89c0 >> 2),
837 0x00000000,
838 (0x0e00 << 16) | (0x88c4 >> 2),
839 0x00000000,
840 (0x0e00 << 16) | (0x88c8 >> 2),
841 0x00000000,
842 (0x0e00 << 16) | (0x88d0 >> 2),
843 0x00000000,
844 (0x0e00 << 16) | (0x88d4 >> 2),
845 0x00000000,
846 (0x0e00 << 16) | (0x88d8 >> 2),
847 0x00000000,
848 (0x0e00 << 16) | (0x8980 >> 2),
849 0x00000000,
850 (0x0e00 << 16) | (0x30938 >> 2),
851 0x00000000,
852 (0x0e00 << 16) | (0x3093c >> 2),
853 0x00000000,
854 (0x0e00 << 16) | (0x30940 >> 2),
855 0x00000000,
856 (0x0e00 << 16) | (0x89a0 >> 2),
857 0x00000000,
858 (0x0e00 << 16) | (0x30900 >> 2),
859 0x00000000,
860 (0x0e00 << 16) | (0x30904 >> 2),
861 0x00000000,
862 (0x0e00 << 16) | (0x89b4 >> 2),
863 0x00000000,
864 (0x0e00 << 16) | (0x3e1fc >> 2),
865 0x00000000,
866 (0x0e00 << 16) | (0x3c210 >> 2),
867 0x00000000,
868 (0x0e00 << 16) | (0x3c214 >> 2),
869 0x00000000,
870 (0x0e00 << 16) | (0x3c218 >> 2),
871 0x00000000,
872 (0x0e00 << 16) | (0x8904 >> 2),
873 0x00000000,
874 0x5,
875 (0x0e00 << 16) | (0x8c28 >> 2),
876 (0x0e00 << 16) | (0x8c2c >> 2),
877 (0x0e00 << 16) | (0x8c30 >> 2),
878 (0x0e00 << 16) | (0x8c34 >> 2),
879 (0x0e00 << 16) | (0x9600 >> 2),
907 * Returns 0 on success, error on failure.
1012 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
1013 tile[reg_offset] = 0; in gfx_v7_0_tiling_mode_table_init()
1014 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
1015 macrotile[reg_offset] = 0; in gfx_v7_0_tiling_mode_table_init()
1019 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1122 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1179 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
1181 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
1186 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1305 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1362 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
1364 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
1372 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1475 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1532 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
1534 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
1548 * 0xffffffff means broadcast to all SEs or SHs (CIK).
1558 if (instance == 0xffffffff) in gfx_v7_0_select_se_sh()
1559 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v7_0_select_se_sh()
1561 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v7_0_select_se_sh()
1563 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v7_0_select_se_sh()
1566 else if (se_num == 0xffffffff) in gfx_v7_0_select_se_sh()
1569 else if (sh_num == 0xffffffff) in gfx_v7_0_select_se_sh()
1609 *rconf1 |= 0x0; in gfx_v7_0_raster_config()
1621 *rconf1 |= 0x0; in gfx_v7_0_raster_config()
1625 *rconf |= 0x0; in gfx_v7_0_raster_config()
1626 *rconf1 |= 0x0; in gfx_v7_0_raster_config()
1629 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); in gfx_v7_0_raster_config()
1646 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; in gfx_v7_0_write_harvested_raster_configs()
1647 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; in gfx_v7_0_write_harvested_raster_configs()
1655 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || in gfx_v7_0_write_harvested_raster_configs()
1659 if (!se_mask[0] && !se_mask[1]) { in gfx_v7_0_write_harvested_raster_configs()
1668 for (se = 0; se < num_se; se++) { in gfx_v7_0_write_harvested_raster_configs()
1734 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_write_harvested_raster_configs()
1740 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_write_harvested_raster_configs()
1754 u32 raster_config = 0, raster_config_1 = 0; in gfx_v7_0_setup_rb()
1755 u32 active_rbs = 0; in gfx_v7_0_setup_rb()
1761 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_setup_rb()
1762 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1763 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v7_0_setup_rb()
1769 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_setup_rb()
1790 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_setup_rb()
1791 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1792 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v7_0_setup_rb()
1803 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_setup_rb()
1807 #define DEFAULT_SH_MEM_BASES (0x6000)
1824 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) in gfx_v7_0_init_compute_vmid()
1825 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) in gfx_v7_0_init_compute_vmid()
1826 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) in gfx_v7_0_init_compute_vmid()
1834 cik_srbm_select(adev, 0, 0, 0, i); in gfx_v7_0_init_compute_vmid()
1838 WREG32(mmSH_MEM_APE1_LIMIT, 0); in gfx_v7_0_init_compute_vmid()
1841 cik_srbm_select(adev, 0, 0, 0, 0); in gfx_v7_0_init_compute_vmid()
1847 WREG32(amdgpu_gds_reg_offset[i].mem_base, 0); in gfx_v7_0_init_compute_vmid()
1848 WREG32(amdgpu_gds_reg_offset[i].mem_size, 0); in gfx_v7_0_init_compute_vmid()
1849 WREG32(amdgpu_gds_reg_offset[i].gws, 0); in gfx_v7_0_init_compute_vmid()
1850 WREG32(amdgpu_gds_reg_offset[i].oa, 0); in gfx_v7_0_init_compute_vmid()
1865 WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0); in gfx_v7_0_init_gds_vmid()
1866 WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0); in gfx_v7_0_init_gds_vmid()
1867 WREG32(amdgpu_gds_reg_offset[vmid].gws, 0); in gfx_v7_0_init_gds_vmid()
1868 WREG32(amdgpu_gds_reg_offset[vmid].oa, 0); in gfx_v7_0_init_gds_vmid()
1891 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); in gfx_v7_0_constants_init()
1905 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | in gfx_v7_0_constants_init()
1906 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); in gfx_v7_0_constants_init()
1913 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_constants_init()
1917 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, in gfx_v7_0_constants_init()
1923 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0); in gfx_v7_0_constants_init()
1925 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG, in gfx_v7_0_constants_init()
1934 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { in gfx_v7_0_constants_init()
1935 if (i == 0) in gfx_v7_0_constants_init()
1936 sh_mem_base = 0; in gfx_v7_0_constants_init()
1939 cik_srbm_select(adev, 0, 0, 0, i); in gfx_v7_0_constants_init()
1943 WREG32(mmSH_MEM_APE1_LIMIT, 0); in gfx_v7_0_constants_init()
1946 cik_srbm_select(adev, 0, 0, 0, 0); in gfx_v7_0_constants_init()
1952 WREG32(mmSX_DEBUG_1, 0x20); in gfx_v7_0_constants_init()
1954 WREG32(mmTA_CNTL_AUX, 0x00010000); in gfx_v7_0_constants_init()
1957 tmp |= 0x03000000; in gfx_v7_0_constants_init()
1962 WREG32(mmDB_DEBUG, 0); in gfx_v7_0_constants_init()
1964 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; in gfx_v7_0_constants_init()
1965 tmp |= 0x00000400; in gfx_v7_0_constants_init()
1968 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; in gfx_v7_0_constants_init()
1969 tmp |= 0x00020200; in gfx_v7_0_constants_init()
1972 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; in gfx_v7_0_constants_init()
1973 tmp |= 0x00018208; in gfx_v7_0_constants_init()
1986 WREG32(mmCP_PERFMON_CNTL, 0); in gfx_v7_0_constants_init()
1988 WREG32(mmSQ_CONFIG, 0); in gfx_v7_0_constants_init()
1999 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); in gfx_v7_0_constants_init()
2025 * Returns 0 on success, error on failure.
2030 uint32_t tmp = 0; in gfx_v7_0_ring_test_ring()
2034 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); in gfx_v7_0_ring_test_ring()
2041 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v7_0_ring_test_ring()
2044 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_ring_test_ring()
2046 if (tmp == 0xDEADBEEF) in gfx_v7_0_ring_test_ring()
2065 int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; in gfx_v7_0_ring_emit_hdp_flush()
2090 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v7_0_ring_emit_hdp_flush()
2095 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v7_0_ring_emit_vgt_flush()
2099 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v7_0_ring_emit_vgt_flush()
2101 EVENT_INDEX(0)); in gfx_v7_0_ring_emit_vgt_flush()
2128 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v7_0_ring_emit_fence_gfx()
2129 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | in gfx_v7_0_ring_emit_fence_gfx()
2130 DATA_SEL(1) | INT_SEL(0)); in gfx_v7_0_ring_emit_fence_gfx()
2140 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v7_0_ring_emit_fence_gfx()
2141 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | in gfx_v7_0_ring_emit_fence_gfx()
2142 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_gfx()
2171 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_compute()
2172 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v7_0_ring_emit_fence_compute()
2201 u32 header, control = 0; in gfx_v7_0_ring_emit_ib_gfx()
2205 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_ib_gfx()
2206 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_ib_gfx()
2219 (2 << 0) | in gfx_v7_0_ring_emit_ib_gfx()
2221 (ib->gpu_addr & 0xFFFFFFFC)); in gfx_v7_0_ring_emit_ib_gfx()
2222 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in gfx_v7_0_ring_emit_ib_gfx()
2242 * GDS to 0 for this ring (me/pipe). in gfx_v7_0_ring_emit_ib_compute()
2253 (2 << 0) | in gfx_v7_0_ring_emit_ib_compute()
2255 (ib->gpu_addr & 0xFFFFFFFC)); in gfx_v7_0_ring_emit_ib_compute()
2256 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in gfx_v7_0_ring_emit_ib_compute()
2262 uint32_t dw2 = 0; in gfx_v7_ring_emit_cntxcntl()
2264 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ in gfx_v7_ring_emit_cntxcntl()
2268 dw2 |= 0x8001; in gfx_v7_ring_emit_cntxcntl()
2270 dw2 |= 0x01000000; in gfx_v7_ring_emit_cntxcntl()
2272 dw2 |= 0x10002; in gfx_v7_ring_emit_cntxcntl()
2277 amdgpu_ring_write(ring, 0); in gfx_v7_ring_emit_cntxcntl()
2288 * Returns 0 on success, error on failure.
2295 uint32_t tmp = 0; in gfx_v7_0_ring_test_ib()
2298 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); in gfx_v7_0_ring_test_ib()
2299 memset(&ib, 0, sizeof(ib)); in gfx_v7_0_ring_test_ib()
2304 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); in gfx_v7_0_ring_test_ib()
2306 ib.ptr[2] = 0xDEADBEEF; in gfx_v7_0_ring_test_ib()
2314 if (r == 0) { in gfx_v7_0_ring_test_ib()
2317 } else if (r < 0) { in gfx_v7_0_ring_test_ib()
2321 if (tmp == 0xDEADBEEF) in gfx_v7_0_ring_test_ib()
2322 r = 0; in gfx_v7_0_ring_test_ib()
2366 WREG32(mmCP_ME_CNTL, 0); in gfx_v7_0_cp_gfx_enable()
2380 * Returns 0 for success, -EINVAL if the ucode is not available.
2414 WREG32(mmCP_PFP_UCODE_ADDR, 0); in gfx_v7_0_cp_gfx_load_microcode()
2415 for (i = 0; i < fw_size; i++) in gfx_v7_0_cp_gfx_load_microcode()
2424 WREG32(mmCP_CE_UCODE_ADDR, 0); in gfx_v7_0_cp_gfx_load_microcode()
2425 for (i = 0; i < fw_size; i++) in gfx_v7_0_cp_gfx_load_microcode()
2434 WREG32(mmCP_ME_RAM_WADDR, 0); in gfx_v7_0_cp_gfx_load_microcode()
2435 for (i = 0; i < fw_size; i++) in gfx_v7_0_cp_gfx_load_microcode()
2439 return 0; in gfx_v7_0_cp_gfx_load_microcode()
2449 * Returns 0 for success, error for failure.
2453 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v7_0_cp_gfx_start()
2460 WREG32(mmCP_ENDIAN_SWAP, 0); in gfx_v7_0_cp_gfx_start()
2474 amdgpu_ring_write(ring, 0x8000); in gfx_v7_0_cp_gfx_start()
2475 amdgpu_ring_write(ring, 0x8000); in gfx_v7_0_cp_gfx_start()
2478 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v7_0_cp_gfx_start()
2482 amdgpu_ring_write(ring, 0x80000000); in gfx_v7_0_cp_gfx_start()
2483 amdgpu_ring_write(ring, 0x80000000); in gfx_v7_0_cp_gfx_start()
2491 for (i = 0; i < ext->reg_count; i++) in gfx_v7_0_cp_gfx_start()
2499 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); in gfx_v7_0_cp_gfx_start()
2500 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v7_0_cp_gfx_start()
2502 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v7_0_cp_gfx_start()
2505 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v7_0_cp_gfx_start()
2506 amdgpu_ring_write(ring, 0); in gfx_v7_0_cp_gfx_start()
2509 amdgpu_ring_write(ring, 0x00000316); in gfx_v7_0_cp_gfx_start()
2510 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ in gfx_v7_0_cp_gfx_start()
2511 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ in gfx_v7_0_cp_gfx_start()
2515 return 0; in gfx_v7_0_cp_gfx_start()
2525 * Returns 0 for success, error for failure.
2535 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); in gfx_v7_0_cp_gfx_resume()
2537 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in gfx_v7_0_cp_gfx_resume()
2540 WREG32(mmCP_RB_WPTR_DELAY, 0); in gfx_v7_0_cp_gfx_resume()
2542 /* set the RB to use vmid 0 */ in gfx_v7_0_cp_gfx_resume()
2543 WREG32(mmCP_RB_VMID, 0); in gfx_v7_0_cp_gfx_resume()
2545 WREG32(mmSCRATCH_ADDR, 0); in gfx_v7_0_cp_gfx_resume()
2547 /* ring 0 - compute and gfx */ in gfx_v7_0_cp_gfx_resume()
2549 ring = &adev->gfx.gfx_ring[0]; in gfx_v7_0_cp_gfx_resume()
2559 ring->wptr = 0; in gfx_v7_0_cp_gfx_resume()
2565 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); in gfx_v7_0_cp_gfx_resume()
2568 WREG32(mmSCRATCH_UMSK, 0); in gfx_v7_0_cp_gfx_resume()
2583 return 0; in gfx_v7_0_cp_gfx_resume()
2632 WREG32(mmCP_MEC_CNTL, 0); in gfx_v7_0_cp_compute_enable()
2645 * Returns 0 for success, -EINVAL if the ucode is not available.
2669 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); in gfx_v7_0_cp_compute_load_microcode()
2670 for (i = 0; i < fw_size; i++) in gfx_v7_0_cp_compute_load_microcode()
2672 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); in gfx_v7_0_cp_compute_load_microcode()
2691 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); in gfx_v7_0_cp_compute_load_microcode()
2692 for (i = 0; i < fw_size; i++) in gfx_v7_0_cp_compute_load_microcode()
2694 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); in gfx_v7_0_cp_compute_load_microcode()
2697 return 0; in gfx_v7_0_cp_compute_load_microcode()
2712 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_fini()
2730 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v7_0_mec_init()
2752 memset(hpd, 0, mec_hpd_size); in gfx_v7_0_mec_init()
2757 return 0; in gfx_v7_0_mec_init()
2809 cik_srbm_select(adev, mec + 1, pipe, 0, 0); in gfx_v7_0_compute_pipe_init()
2816 WREG32(mmCP_HPD_EOP_VMID, 0); in gfx_v7_0_compute_pipe_init()
2824 cik_srbm_select(adev, 0, 0, 0, 0); in gfx_v7_0_compute_pipe_init()
2835 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_mqd_deactivate()
2844 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); in gfx_v7_0_mqd_deactivate()
2845 WREG32(mmCP_HQD_PQ_RPTR, 0); in gfx_v7_0_mqd_deactivate()
2846 WREG32(mmCP_HQD_PQ_WPTR, 0); in gfx_v7_0_mqd_deactivate()
2849 return 0; in gfx_v7_0_mqd_deactivate()
2861 memset(mqd, 0, sizeof(struct cik_mqd)); in gfx_v7_0_mqd_init()
2863 mqd->header = 0xC0310800; in gfx_v7_0_mqd_init()
2864 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; in gfx_v7_0_mqd_init()
2865 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; in gfx_v7_0_mqd_init()
2866 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; in gfx_v7_0_mqd_init()
2867 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; in gfx_v7_0_mqd_init()
2878 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; in gfx_v7_0_mqd_init()
2881 /* set MQD vmid to 0 */ in gfx_v7_0_mqd_init()
2914 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v7_0_mqd_init()
2915 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v7_0_mqd_init()
2919 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v7_0_mqd_init()
2921 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v7_0_mqd_init()
2939 mqd->cp_hqd_pq_doorbell_control = 0; in gfx_v7_0_mqd_init()
2943 ring->wptr = 0; in gfx_v7_0_mqd_init()
2948 mqd->cp_hqd_vmid = 0; in gfx_v7_0_mqd_init()
2983 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v7_0_mqd_commit()
2994 return 0; in gfx_v7_0_mqd_commit()
3013 cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v7_0_compute_queue_init()
3019 cik_srbm_select(adev, 0, 0, 0, 0); in gfx_v7_0_compute_queue_init()
3024 return 0; in gfx_v7_0_compute_queue_init()
3034 * Returns 0 for success, error for failure.
3048 for (i = 0; i < adev->gfx.mec.num_mec; i++) in gfx_v7_0_cp_compute_resume()
3049 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) in gfx_v7_0_cp_compute_resume()
3053 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()
3063 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()
3068 return 0; in gfx_v7_0_cp_compute_resume()
3088 return 0; in gfx_v7_0_cp_load_microcode()
3124 return 0; in gfx_v7_0_cp_resume()
3145 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v7_0_ring_emit_pipeline_sync()
3146 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); in gfx_v7_0_ring_emit_pipeline_sync()
3148 amdgpu_ring_write(ring, 0xffffffff); in gfx_v7_0_ring_emit_pipeline_sync()
3153 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_pipeline_sync()
3154 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_pipeline_sync()
3155 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_pipeline_sync()
3156 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_pipeline_sync()
3162 * VMID 0 is the physical GPU addresses as used by the kernel.
3185 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ in gfx_v7_0_ring_emit_vm_flush()
3186 WAIT_REG_MEM_FUNCTION(0) | /* always */ in gfx_v7_0_ring_emit_vm_flush()
3187 WAIT_REG_MEM_ENGINE(0))); /* me */ in gfx_v7_0_ring_emit_vm_flush()
3189 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_vm_flush()
3190 amdgpu_ring_write(ring, 0); /* ref */ in gfx_v7_0_ring_emit_vm_flush()
3191 amdgpu_ring_write(ring, 0); /* mask */ in gfx_v7_0_ring_emit_vm_flush()
3192 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v7_0_ring_emit_vm_flush()
3197 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in gfx_v7_0_ring_emit_vm_flush()
3198 amdgpu_ring_write(ring, 0x0); in gfx_v7_0_ring_emit_vm_flush()
3201 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_vm_flush()
3202 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_vm_flush()
3203 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_vm_flush()
3204 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_vm_flush()
3215 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_wreg()
3217 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_wreg()
3275 /* init spm vmid with 0xf */ in gfx_v7_0_rlc_init()
3277 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); in gfx_v7_0_rlc_init()
3279 return 0; in gfx_v7_0_rlc_init()
3300 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_wait_for_rlc_serdes()
3301 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_wait_for_rlc_serdes()
3302 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v7_0_wait_for_rlc_serdes()
3303 for (k = 0; k < adev->usec_timeout; k++) { in gfx_v7_0_wait_for_rlc_serdes()
3304 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) in gfx_v7_0_wait_for_rlc_serdes()
3310 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_wait_for_rlc_serdes()
3317 for (k = 0; k < adev->usec_timeout; k++) { in gfx_v7_0_wait_for_rlc_serdes()
3318 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) in gfx_v7_0_wait_for_rlc_serdes()
3345 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_halt_rlc()
3346 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) in gfx_v7_0_halt_rlc()
3366 tmp = 0x1 | (1 << 1); in gfx_v7_0_set_safe_mode()
3371 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_set_safe_mode()
3377 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_set_safe_mode()
3378 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) in gfx_v7_0_set_safe_mode()
3388 tmp = 0x1 | (0 << 1); in gfx_v7_0_unset_safe_mode()
3401 WREG32(mmRLC_CNTL, 0); in gfx_v7_0_rlc_stop()
3443 * Returns 0 for success, -EINVAL if the ucode is not available.
3464 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; in gfx_v7_0_rlc_resume()
3471 WREG32(mmRLC_LB_CNTR_INIT, 0); in gfx_v7_0_rlc_resume()
3472 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000); in gfx_v7_0_rlc_resume()
3475 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_rlc_resume()
3476 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); in gfx_v7_0_rlc_resume()
3477 WREG32(mmRLC_LB_PARAMS, 0x00600408); in gfx_v7_0_rlc_resume()
3478 WREG32(mmRLC_LB_CNTL, 0x80000004); in gfx_v7_0_rlc_resume()
3481 WREG32(mmRLC_MC_CNTL, 0); in gfx_v7_0_rlc_resume()
3482 WREG32(mmRLC_UCODE_CNTL, 0); in gfx_v7_0_rlc_resume()
3487 WREG32(mmRLC_GPM_UCODE_ADDR, 0); in gfx_v7_0_rlc_resume()
3488 for (i = 0; i < fw_size; i++) in gfx_v7_0_rlc_resume()
3496 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0); in gfx_v7_0_rlc_resume()
3500 return 0; in gfx_v7_0_rlc_resume()
3531 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_enable_cgcg()
3532 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_cgcg()
3533 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_cgcg()
3564 u32 data, orig, tmp = 0; in gfx_v7_0_enable_mgcg()
3577 data |= 0x00000001; in gfx_v7_0_enable_mgcg()
3578 data &= 0xfffffffd; in gfx_v7_0_enable_mgcg()
3585 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_enable_mgcg()
3586 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_mgcg()
3587 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_mgcg()
3598 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); in gfx_v7_0_enable_mgcg()
3606 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); in gfx_v7_0_enable_mgcg()
3612 data |= 0x00000003; in gfx_v7_0_enable_mgcg()
3636 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_enable_mgcg()
3637 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_mgcg()
3638 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_mgcg()
3696 data &= ~0x8000; in gfx_v7_0_enable_cp_pg()
3698 data |= 0x8000; in gfx_v7_0_enable_cp_pg()
3709 data &= ~0x2000; in gfx_v7_0_enable_gds_pg()
3711 data |= 0x2000; in gfx_v7_0_enable_gds_pg()
3823 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
3824 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
3838 for (i = 0; i < 3; i++) in gfx_v7_0_init_gfx_cgpg()
3839 WREG32(mmRLC_GPM_SCRATCH_DATA, 0); in gfx_v7_0_init_gfx_cgpg()
3843 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) in gfx_v7_0_init_gfx_cgpg()
3857 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v7_0_init_gfx_cgpg()
3860 data = 0x10101010; in gfx_v7_0_init_gfx_cgpg()
3864 data &= ~0xff; in gfx_v7_0_init_gfx_cgpg()
3865 data |= 0x3; in gfx_v7_0_init_gfx_cgpg()
3870 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); in gfx_v7_0_init_gfx_cgpg()
3884 u32 count = 0; in gfx_v7_0_get_csb_size()
3889 return 0; in gfx_v7_0_get_csb_size()
3901 return 0; in gfx_v7_0_get_csb_size()
3917 u32 count = 0, i; in gfx_v7_0_get_csb_buffer()
3926 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v7_0_get_csb_buffer()
3930 buffer[count++] = cpu_to_le32(0x80000000); in gfx_v7_0_get_csb_buffer()
3931 buffer[count++] = cpu_to_le32(0x80000000); in gfx_v7_0_get_csb_buffer()
3939 for (i = 0; i < ext->reg_count; i++) in gfx_v7_0_get_csb_buffer()
3951 buffer[count++] = cpu_to_le32(0x16000012); in gfx_v7_0_get_csb_buffer()
3952 buffer[count++] = cpu_to_le32(0x00000000); in gfx_v7_0_get_csb_buffer()
3955 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ in gfx_v7_0_get_csb_buffer()
3956 buffer[count++] = cpu_to_le32(0x00000000); in gfx_v7_0_get_csb_buffer()
3960 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ in gfx_v7_0_get_csb_buffer()
3961 buffer[count++] = cpu_to_le32(0x00000000); in gfx_v7_0_get_csb_buffer()
3964 buffer[count++] = cpu_to_le32(0x3a00161a); in gfx_v7_0_get_csb_buffer()
3965 buffer[count++] = cpu_to_le32(0x0000002e); in gfx_v7_0_get_csb_buffer()
3968 buffer[count++] = cpu_to_le32(0x00000000); in gfx_v7_0_get_csb_buffer()
3969 buffer[count++] = cpu_to_le32(0x00000000); in gfx_v7_0_get_csb_buffer()
3973 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v7_0_get_csb_buffer()
3976 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v7_0_get_csb_buffer()
3977 buffer[count++] = cpu_to_le32(0); in gfx_v7_0_get_csb_buffer()
4044 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v7_0_ring_emit_gds_switch()
4045 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
4047 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_gds_switch()
4052 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v7_0_ring_emit_gds_switch()
4053 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
4055 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_gds_switch()
4060 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v7_0_ring_emit_gds_switch()
4061 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
4063 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_gds_switch()
4068 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v7_0_ring_emit_gds_switch()
4069 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
4071 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_gds_switch()
4078 uint32_t value = 0; in gfx_v7_0_ring_soft_recovery()
4080 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); in gfx_v7_0_ring_soft_recovery()
4081 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); in gfx_v7_0_ring_soft_recovery()
4114 /* type 0 wave data */ in gfx_v7_0_read_wave_data()
4115 dst[(*no_fields)++] = 0; in gfx_v7_0_read_wave_data()
4142 adev, simd, wave, 0, in gfx_v7_0_read_wave_sgprs()
4189 return 0; in gfx_v7_0_early_init()
4197 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v7_0_late_init()
4201 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v7_0_late_init()
4205 return 0; in gfx_v7_0_late_init()
4227 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4228 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4229 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4230 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4244 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4245 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4246 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4247 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4261 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4262 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4263 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4264 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4280 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4281 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4282 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4283 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4309 …if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map… in gfx_v7_0_gpu_early_init()
4310 dimm00_addr_map = 0; in gfx_v7_0_gpu_early_init()
4311 …if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map… in gfx_v7_0_gpu_early_init()
4312 dimm01_addr_map = 0; in gfx_v7_0_gpu_early_init()
4313 …if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map… in gfx_v7_0_gpu_early_init()
4314 dimm10_addr_map = 0; in gfx_v7_0_gpu_early_init()
4315 …if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map… in gfx_v7_0_gpu_early_init()
4316 dimm11_addr_map = 0; in gfx_v7_0_gpu_early_init()
4340 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); in gfx_v7_0_gpu_early_init()
4381 return 0; in gfx_v7_0_compute_ring_init()
4441 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v7_0_sw_init()
4454 ring_id = 0; in gfx_v7_0_sw_init()
4455 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v7_0_sw_init()
4456 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v7_0_sw_init()
4457 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v7_0_sw_init()
4458 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, in gfx_v7_0_sw_init()
4473 adev->gfx.ce_ram_size = 0x8000; in gfx_v7_0_sw_init()
4485 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_sw_fini()
4487 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_sw_fini()
4503 return 0; in gfx_v7_0_sw_fini()
4531 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v7_0_hw_fini()
4532 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v7_0_hw_fini()
4537 return 0; in gfx_v7_0_hw_fini()
4570 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_wait_for_idle()
4575 return 0; in gfx_v7_0_wait_for_idle()
4583 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; in gfx_v7_0_soft_reset()
4630 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in gfx_v7_0_soft_reset()
4644 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in gfx_v7_0_soft_reset()
4657 return 0; in gfx_v7_0_soft_reset()
4695 case 0: in gfx_v7_0_set_compute_eop_interrupt_state()
4754 return 0; in gfx_v7_0_set_priv_reg_fault_state()
4779 return 0; in gfx_v7_0_set_priv_inst_fault_state()
4792 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state); in gfx_v7_0_set_eop_interrupt_state()
4804 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state); in gfx_v7_0_set_eop_interrupt_state()
4818 return 0; in gfx_v7_0_set_eop_interrupt_state()
4830 me_id = (entry->ring_id & 0x0c) >> 2; in gfx_v7_0_eop_irq()
4831 pipe_id = (entry->ring_id & 0x03) >> 0; in gfx_v7_0_eop_irq()
4833 case 0: in gfx_v7_0_eop_irq()
4834 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v7_0_eop_irq()
4838 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_eop_irq()
4845 return 0; in gfx_v7_0_eop_irq()
4855 me_id = (entry->ring_id & 0x0c) >> 2; in gfx_v7_0_fault()
4856 pipe_id = (entry->ring_id & 0x03) >> 0; in gfx_v7_0_fault()
4858 case 0: in gfx_v7_0_fault()
4859 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); in gfx_v7_0_fault()
4863 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_fault()
4878 return 0; in gfx_v7_0_priv_reg_irq()
4888 return 0; in gfx_v7_0_priv_inst_irq()
4911 return 0; in gfx_v7_0_set_clockgating_state()
4936 return 0; in gfx_v7_0_set_powergating_state()
4946 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ in gfx_v7_0_emit_mem_sync()
4947 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ in gfx_v7_0_emit_mem_sync()
4948 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ in gfx_v7_0_emit_mem_sync()
4958 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ in gfx_v7_0_emit_mem_sync_compute()
4959 amdgpu_ring_write(ring, 0xff); /* CP_COHER_SIZE_HI */ in gfx_v7_0_emit_mem_sync_compute()
4960 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ in gfx_v7_0_emit_mem_sync_compute()
4961 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ in gfx_v7_0_emit_mem_sync_compute()
4962 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ in gfx_v7_0_emit_mem_sync_compute()
4984 .align_mask = 0xff,
4985 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5018 .align_mask = 0xff,
5019 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5051 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_set_ring_funcs()
5053 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_set_ring_funcs()
5096 int i, j, k, counter, active_cu_number = 0; in gfx_v7_0_get_cu_info()
5097 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; in gfx_v7_0_get_cu_info()
5107 memset(cu_info, 0, sizeof(*cu_info)); in gfx_v7_0_get_cu_info()
5112 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_get_cu_info()
5113 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_get_cu_info()
5115 ao_bitmap = 0; in gfx_v7_0_get_cu_info()
5116 counter = 0; in gfx_v7_0_get_cu_info()
5117 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v7_0_get_cu_info()
5122 cu_info->bitmap[0][i][j] = bitmap; in gfx_v7_0_get_cu_info()
5124 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v7_0_get_cu_info()
5138 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_get_cu_info()
5154 .rev = 0,
5162 .rev = 0,
5170 .rev = 0,