3202 	u32 cp_int_cntl;  in gfx_v6_0_set_gfx_eop_interrupt_state()  local
3206 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);  in gfx_v6_0_set_gfx_eop_interrupt_state()
3207 		cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;  in gfx_v6_0_set_gfx_eop_interrupt_state()
3208 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);  in gfx_v6_0_set_gfx_eop_interrupt_state()
3211 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);  in gfx_v6_0_set_gfx_eop_interrupt_state()
3212 		cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;  in gfx_v6_0_set_gfx_eop_interrupt_state()
3213 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);  in gfx_v6_0_set_gfx_eop_interrupt_state()
3224 	u32 cp_int_cntl;  in gfx_v6_0_set_compute_eop_interrupt_state()  local
3228 			cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);  in gfx_v6_0_set_compute_eop_interrupt_state()
3229 			cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;  in gfx_v6_0_set_compute_eop_interrupt_state()
3230 			WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);  in gfx_v6_0_set_compute_eop_interrupt_state()
3233 			cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);  in gfx_v6_0_set_compute_eop_interrupt_state()
3234 			cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;  in gfx_v6_0_set_compute_eop_interrupt_state()
3235 			WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);  in gfx_v6_0_set_compute_eop_interrupt_state()
3241 			cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);  in gfx_v6_0_set_compute_eop_interrupt_state()
3242 			cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;  in gfx_v6_0_set_compute_eop_interrupt_state()
3243 			WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);  in gfx_v6_0_set_compute_eop_interrupt_state()
3246 			cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);  in gfx_v6_0_set_compute_eop_interrupt_state()
3247 			cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;  in gfx_v6_0_set_compute_eop_interrupt_state()
3248 			WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);  in gfx_v6_0_set_compute_eop_interrupt_state()
3265 	u32 cp_int_cntl;  in gfx_v6_0_set_priv_reg_fault_state()  local
3269 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);  in gfx_v6_0_set_priv_reg_fault_state()
3270 		cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;  in gfx_v6_0_set_priv_reg_fault_state()
3271 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);  in gfx_v6_0_set_priv_reg_fault_state()
3274 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);  in gfx_v6_0_set_priv_reg_fault_state()
3275 		cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;  in gfx_v6_0_set_priv_reg_fault_state()
3276 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);  in gfx_v6_0_set_priv_reg_fault_state()
3290 	u32 cp_int_cntl;  in gfx_v6_0_set_priv_inst_fault_state()  local
3294 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);  in gfx_v6_0_set_priv_inst_fault_state()
3295 		cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;  in gfx_v6_0_set_priv_inst_fault_state()
3296 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);  in gfx_v6_0_set_priv_inst_fault_state()
3299 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);  in gfx_v6_0_set_priv_inst_fault_state()
3300 		cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;  in gfx_v6_0_set_priv_inst_fault_state()
3301 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);  in gfx_v6_0_set_priv_inst_fault_state()