Lines Matching +full:0 +full:x8c20
82 #define MICRO_TILE_MODE(x) ((x) << 0)
91 (0x8000 << 16) | (0x98f4 >> 2),
92 0x00000000,
93 (0x8040 << 16) | (0x98f4 >> 2),
94 0x00000000,
95 (0x8000 << 16) | (0xe80 >> 2),
96 0x00000000,
97 (0x8040 << 16) | (0xe80 >> 2),
98 0x00000000,
99 (0x8000 << 16) | (0x89bc >> 2),
100 0x00000000,
101 (0x8040 << 16) | (0x89bc >> 2),
102 0x00000000,
103 (0x8000 << 16) | (0x8c1c >> 2),
104 0x00000000,
105 (0x8040 << 16) | (0x8c1c >> 2),
106 0x00000000,
107 (0x9c00 << 16) | (0x98f0 >> 2),
108 0x00000000,
109 (0x9c00 << 16) | (0xe7c >> 2),
110 0x00000000,
111 (0x8000 << 16) | (0x9148 >> 2),
112 0x00000000,
113 (0x8040 << 16) | (0x9148 >> 2),
114 0x00000000,
115 (0x9c00 << 16) | (0x9150 >> 2),
116 0x00000000,
117 (0x9c00 << 16) | (0x897c >> 2),
118 0x00000000,
119 (0x9c00 << 16) | (0x8d8c >> 2),
120 0x00000000,
121 (0x9c00 << 16) | (0xac54 >> 2),
122 0X00000000,
123 0x3,
124 (0x9c00 << 16) | (0x98f8 >> 2),
125 0x00000000,
126 (0x9c00 << 16) | (0x9910 >> 2),
127 0x00000000,
128 (0x9c00 << 16) | (0x9914 >> 2),
129 0x00000000,
130 (0x9c00 << 16) | (0x9918 >> 2),
131 0x00000000,
132 (0x9c00 << 16) | (0x991c >> 2),
133 0x00000000,
134 (0x9c00 << 16) | (0x9920 >> 2),
135 0x00000000,
136 (0x9c00 << 16) | (0x9924 >> 2),
137 0x00000000,
138 (0x9c00 << 16) | (0x9928 >> 2),
139 0x00000000,
140 (0x9c00 << 16) | (0x992c >> 2),
141 0x00000000,
142 (0x9c00 << 16) | (0x9930 >> 2),
143 0x00000000,
144 (0x9c00 << 16) | (0x9934 >> 2),
145 0x00000000,
146 (0x9c00 << 16) | (0x9938 >> 2),
147 0x00000000,
148 (0x9c00 << 16) | (0x993c >> 2),
149 0x00000000,
150 (0x9c00 << 16) | (0x9940 >> 2),
151 0x00000000,
152 (0x9c00 << 16) | (0x9944 >> 2),
153 0x00000000,
154 (0x9c00 << 16) | (0x9948 >> 2),
155 0x00000000,
156 (0x9c00 << 16) | (0x994c >> 2),
157 0x00000000,
158 (0x9c00 << 16) | (0x9950 >> 2),
159 0x00000000,
160 (0x9c00 << 16) | (0x9954 >> 2),
161 0x00000000,
162 (0x9c00 << 16) | (0x9958 >> 2),
163 0x00000000,
164 (0x9c00 << 16) | (0x995c >> 2),
165 0x00000000,
166 (0x9c00 << 16) | (0x9960 >> 2),
167 0x00000000,
168 (0x9c00 << 16) | (0x9964 >> 2),
169 0x00000000,
170 (0x9c00 << 16) | (0x9968 >> 2),
171 0x00000000,
172 (0x9c00 << 16) | (0x996c >> 2),
173 0x00000000,
174 (0x9c00 << 16) | (0x9970 >> 2),
175 0x00000000,
176 (0x9c00 << 16) | (0x9974 >> 2),
177 0x00000000,
178 (0x9c00 << 16) | (0x9978 >> 2),
179 0x00000000,
180 (0x9c00 << 16) | (0x997c >> 2),
181 0x00000000,
182 (0x9c00 << 16) | (0x9980 >> 2),
183 0x00000000,
184 (0x9c00 << 16) | (0x9984 >> 2),
185 0x00000000,
186 (0x9c00 << 16) | (0x9988 >> 2),
187 0x00000000,
188 (0x9c00 << 16) | (0x998c >> 2),
189 0x00000000,
190 (0x9c00 << 16) | (0x8c00 >> 2),
191 0x00000000,
192 (0x9c00 << 16) | (0x8c14 >> 2),
193 0x00000000,
194 (0x9c00 << 16) | (0x8c04 >> 2),
195 0x00000000,
196 (0x9c00 << 16) | (0x8c08 >> 2),
197 0x00000000,
198 (0x8000 << 16) | (0x9b7c >> 2),
199 0x00000000,
200 (0x8040 << 16) | (0x9b7c >> 2),
201 0x00000000,
202 (0x8000 << 16) | (0xe84 >> 2),
203 0x00000000,
204 (0x8040 << 16) | (0xe84 >> 2),
205 0x00000000,
206 (0x8000 << 16) | (0x89c0 >> 2),
207 0x00000000,
208 (0x8040 << 16) | (0x89c0 >> 2),
209 0x00000000,
210 (0x8000 << 16) | (0x914c >> 2),
211 0x00000000,
212 (0x8040 << 16) | (0x914c >> 2),
213 0x00000000,
214 (0x8000 << 16) | (0x8c20 >> 2),
215 0x00000000,
216 (0x8040 << 16) | (0x8c20 >> 2),
217 0x00000000,
218 (0x8000 << 16) | (0x9354 >> 2),
219 0x00000000,
220 (0x8040 << 16) | (0x9354 >> 2),
221 0x00000000,
222 (0x9c00 << 16) | (0x9060 >> 2),
223 0x00000000,
224 (0x9c00 << 16) | (0x9364 >> 2),
225 0x00000000,
226 (0x9c00 << 16) | (0x9100 >> 2),
227 0x00000000,
228 (0x9c00 << 16) | (0x913c >> 2),
229 0x00000000,
230 (0x8000 << 16) | (0x90e0 >> 2),
231 0x00000000,
232 (0x8000 << 16) | (0x90e4 >> 2),
233 0x00000000,
234 (0x8000 << 16) | (0x90e8 >> 2),
235 0x00000000,
236 (0x8040 << 16) | (0x90e0 >> 2),
237 0x00000000,
238 (0x8040 << 16) | (0x90e4 >> 2),
239 0x00000000,
240 (0x8040 << 16) | (0x90e8 >> 2),
241 0x00000000,
242 (0x9c00 << 16) | (0x8bcc >> 2),
243 0x00000000,
244 (0x9c00 << 16) | (0x8b24 >> 2),
245 0x00000000,
246 (0x9c00 << 16) | (0x88c4 >> 2),
247 0x00000000,
248 (0x9c00 << 16) | (0x8e50 >> 2),
249 0x00000000,
250 (0x9c00 << 16) | (0x8c0c >> 2),
251 0x00000000,
252 (0x9c00 << 16) | (0x8e58 >> 2),
253 0x00000000,
254 (0x9c00 << 16) | (0x8e5c >> 2),
255 0x00000000,
256 (0x9c00 << 16) | (0x9508 >> 2),
257 0x00000000,
258 (0x9c00 << 16) | (0x950c >> 2),
259 0x00000000,
260 (0x9c00 << 16) | (0x9494 >> 2),
261 0x00000000,
262 (0x9c00 << 16) | (0xac0c >> 2),
263 0x00000000,
264 (0x9c00 << 16) | (0xac10 >> 2),
265 0x00000000,
266 (0x9c00 << 16) | (0xac14 >> 2),
267 0x00000000,
268 (0x9c00 << 16) | (0xae00 >> 2),
269 0x00000000,
270 (0x9c00 << 16) | (0xac08 >> 2),
271 0x00000000,
272 (0x9c00 << 16) | (0x88d4 >> 2),
273 0x00000000,
274 (0x9c00 << 16) | (0x88c8 >> 2),
275 0x00000000,
276 (0x9c00 << 16) | (0x88cc >> 2),
277 0x00000000,
278 (0x9c00 << 16) | (0x89b0 >> 2),
279 0x00000000,
280 (0x9c00 << 16) | (0x8b10 >> 2),
281 0x00000000,
282 (0x9c00 << 16) | (0x8a14 >> 2),
283 0x00000000,
284 (0x9c00 << 16) | (0x9830 >> 2),
285 0x00000000,
286 (0x9c00 << 16) | (0x9834 >> 2),
287 0x00000000,
288 (0x9c00 << 16) | (0x9838 >> 2),
289 0x00000000,
290 (0x9c00 << 16) | (0x9a10 >> 2),
291 0x00000000,
292 (0x8000 << 16) | (0x9870 >> 2),
293 0x00000000,
294 (0x8000 << 16) | (0x9874 >> 2),
295 0x00000000,
296 (0x8001 << 16) | (0x9870 >> 2),
297 0x00000000,
298 (0x8001 << 16) | (0x9874 >> 2),
299 0x00000000,
300 (0x8040 << 16) | (0x9870 >> 2),
301 0x00000000,
302 (0x8040 << 16) | (0x9874 >> 2),
303 0x00000000,
304 (0x8041 << 16) | (0x9870 >> 2),
305 0x00000000,
306 (0x8041 << 16) | (0x9874 >> 2),
307 0x00000000,
308 0x00000000
388 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); in gfx_v6_0_tiling_mode_table_init()
405 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | in gfx_v6_0_tiling_mode_table_init()
626 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()
629 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | in gfx_v6_0_tiling_mode_table_init()
832 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()
835 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | in gfx_v6_0_tiling_mode_table_init()
1056 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()
1059 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | in gfx_v6_0_tiling_mode_table_init()
1280 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()
1283 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); in gfx_v6_0_tiling_mode_table_init()
1292 if (instance == 0xffffffff) in gfx_v6_0_select_se_sh()
1293 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v6_0_select_se_sh()
1295 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v6_0_select_se_sh()
1297 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v6_0_select_se_sh()
1300 else if (se_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1303 else if (sh_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1351 *rconf |= 0x0; in gfx_v6_0_raster_config()
1354 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); in gfx_v6_0_raster_config()
1370 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; in gfx_v6_0_write_harvested_raster_configs()
1371 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; in gfx_v6_0_write_harvested_raster_configs()
1379 for (se = 0; se < num_se; se++) { in gfx_v6_0_write_harvested_raster_configs()
1441 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0); in gfx_v6_0_write_harvested_raster_configs()
1446 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v6_0_write_harvested_raster_configs()
1453 u32 raster_config = 0; in gfx_v6_0_setup_rb()
1454 u32 active_rbs = 0; in gfx_v6_0_setup_rb()
1460 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v6_0_setup_rb()
1461 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()
1462 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v6_0_setup_rb()
1469 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v6_0_setup_rb()
1488 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v6_0_setup_rb()
1489 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()
1490 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v6_0_setup_rb()
1499 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v6_0_setup_rb()
1533 u32 active_cu = 0; in gfx_v6_0_setup_spi()
1536 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v6_0_setup_spi()
1537 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_spi()
1538 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v6_0_setup_spi()
1543 for (k = 0; k < 16; k++) { in gfx_v6_0_setup_spi()
1553 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v6_0_setup_spi()
1559 adev->gfx.config.double_offchip_lds_buf = 0; in gfx_v6_0_config_init()
1564 u32 gb_addr_config = 0; in gfx_v6_0_constants_init()
1582 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1583 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v6_0_constants_init()
1584 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1585 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1599 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1600 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v6_0_constants_init()
1601 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1602 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1616 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1617 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; in gfx_v6_0_constants_init()
1618 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1619 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1633 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1634 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; in gfx_v6_0_constants_init()
1635 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1636 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1650 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1651 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; in gfx_v6_0_constants_init()
1652 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1653 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1661 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); in gfx_v6_0_constants_init()
1684 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; in gfx_v6_0_constants_init()
1705 #if 0 in gfx_v6_0_constants_init()
1721 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | in gfx_v6_0_constants_init()
1722 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); in gfx_v6_0_constants_init()
1723 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | in gfx_v6_0_constants_init()
1724 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); in gfx_v6_0_constants_init()
1737 WREG32(mmCP_PERFMON_CNTL, 0); in gfx_v6_0_constants_init()
1738 WREG32(mmSQ_CONFIG, 0); in gfx_v6_0_constants_init()
1747 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); in gfx_v6_0_constants_init()
1749 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0); in gfx_v6_0_constants_init()
1750 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0); in gfx_v6_0_constants_init()
1751 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0); in gfx_v6_0_constants_init()
1752 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0); in gfx_v6_0_constants_init()
1753 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0); in gfx_v6_0_constants_init()
1754 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0); in gfx_v6_0_constants_init()
1755 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0); in gfx_v6_0_constants_init()
1756 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0); in gfx_v6_0_constants_init()
1770 uint32_t tmp = 0; in gfx_v6_0_ring_test_ring()
1774 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); in gfx_v6_0_ring_test_ring()
1782 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v6_0_ring_test_ring()
1785 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v6_0_ring_test_ring()
1787 if (tmp == 0xDEADBEEF) in gfx_v6_0_ring_test_ring()
1799 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v6_0_ring_emit_vgt_flush()
1801 EVENT_INDEX(0)); in gfx_v6_0_ring_emit_vgt_flush()
1812 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_fence()
1818 amdgpu_ring_write(ring, 0xFFFFFFFF); in gfx_v6_0_ring_emit_fence()
1819 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_fence()
1824 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v6_0_ring_emit_fence()
1825 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | in gfx_v6_0_ring_emit_fence()
1827 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); in gfx_v6_0_ring_emit_fence()
1838 u32 header, control = 0; in gfx_v6_0_ring_emit_ib()
1842 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v6_0_ring_emit_ib()
1843 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_ib()
1856 (2 << 0) | in gfx_v6_0_ring_emit_ib()
1858 (ib->gpu_addr & 0xFFFFFFFC)); in gfx_v6_0_ring_emit_ib()
1859 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in gfx_v6_0_ring_emit_ib()
1871 * Returns 0 on success, error on failure.
1878 uint32_t tmp = 0; in gfx_v6_0_ring_test_ib()
1881 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); in gfx_v6_0_ring_test_ib()
1882 memset(&ib, 0, sizeof(ib)); in gfx_v6_0_ring_test_ib()
1887 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); in gfx_v6_0_ring_test_ib()
1889 ib.ptr[2] = 0xDEADBEEF; in gfx_v6_0_ring_test_ib()
1897 if (r == 0) { in gfx_v6_0_ring_test_ib()
1900 } else if (r < 0) { in gfx_v6_0_ring_test_ib()
1904 if (tmp == 0xDEADBEEF) in gfx_v6_0_ring_test_ib()
1905 r = 0; in gfx_v6_0_ring_test_ib()
1918 WREG32(mmCP_ME_CNTL, 0); in gfx_v6_0_cp_gfx_enable()
1923 WREG32(mmSCRATCH_UMSK, 0); in gfx_v6_0_cp_gfx_enable()
1953 WREG32(mmCP_PFP_UCODE_ADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1954 for (i = 0; i < fw_size; i++) in gfx_v6_0_cp_gfx_load_microcode()
1956 WREG32(mmCP_PFP_UCODE_ADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1962 WREG32(mmCP_CE_UCODE_ADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1963 for (i = 0; i < fw_size; i++) in gfx_v6_0_cp_gfx_load_microcode()
1965 WREG32(mmCP_CE_UCODE_ADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1971 WREG32(mmCP_ME_RAM_WADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1972 for (i = 0; i < fw_size; i++) in gfx_v6_0_cp_gfx_load_microcode()
1974 WREG32(mmCP_ME_RAM_WADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1976 WREG32(mmCP_PFP_UCODE_ADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1977 WREG32(mmCP_CE_UCODE_ADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1978 WREG32(mmCP_ME_RAM_WADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1979 WREG32(mmCP_ME_RAM_RADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1980 return 0; in gfx_v6_0_cp_gfx_load_microcode()
1987 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v6_0_cp_gfx_start()
1996 amdgpu_ring_write(ring, 0x1); in gfx_v6_0_cp_gfx_start()
1997 amdgpu_ring_write(ring, 0x0); in gfx_v6_0_cp_gfx_start()
2000 amdgpu_ring_write(ring, 0); in gfx_v6_0_cp_gfx_start()
2001 amdgpu_ring_write(ring, 0); in gfx_v6_0_cp_gfx_start()
2005 amdgpu_ring_write(ring, 0xc000); in gfx_v6_0_cp_gfx_start()
2006 amdgpu_ring_write(ring, 0xe000); in gfx_v6_0_cp_gfx_start()
2017 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v6_0_cp_gfx_start()
2026 for (i = 0; i < ext->reg_count; i++) in gfx_v6_0_cp_gfx_start()
2032 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v6_0_cp_gfx_start()
2035 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v6_0_cp_gfx_start()
2036 amdgpu_ring_write(ring, 0); in gfx_v6_0_cp_gfx_start()
2039 amdgpu_ring_write(ring, 0x00000316); in gfx_v6_0_cp_gfx_start()
2040 amdgpu_ring_write(ring, 0x0000000e); in gfx_v6_0_cp_gfx_start()
2041 amdgpu_ring_write(ring, 0x00000010); in gfx_v6_0_cp_gfx_start()
2045 return 0; in gfx_v6_0_cp_gfx_start()
2056 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); in gfx_v6_0_cp_gfx_resume()
2057 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in gfx_v6_0_cp_gfx_resume()
2060 WREG32(mmCP_RB_WPTR_DELAY, 0); in gfx_v6_0_cp_gfx_resume()
2062 WREG32(mmCP_DEBUG, 0); in gfx_v6_0_cp_gfx_resume()
2063 WREG32(mmSCRATCH_ADDR, 0); in gfx_v6_0_cp_gfx_resume()
2065 /* ring 0 - compute and gfx */ in gfx_v6_0_cp_gfx_resume()
2067 ring = &adev->gfx.gfx_ring[0]; in gfx_v6_0_cp_gfx_resume()
2078 ring->wptr = 0; in gfx_v6_0_cp_gfx_resume()
2084 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); in gfx_v6_0_cp_gfx_resume()
2086 WREG32(mmSCRATCH_UMSK, 0); in gfx_v6_0_cp_gfx_resume()
2099 return 0; in gfx_v6_0_cp_gfx_resume()
2111 if (ring == &adev->gfx.gfx_ring[0]) in gfx_v6_0_ring_get_wptr()
2113 else if (ring == &adev->gfx.compute_ring[0]) in gfx_v6_0_ring_get_wptr()
2133 if (ring == &adev->gfx.compute_ring[0]) { in gfx_v6_0_ring_set_wptr_compute()
2156 ring = &adev->gfx.compute_ring[0]; in gfx_v6_0_cp_compute_resume()
2165 ring->wptr = 0; in gfx_v6_0_cp_compute_resume()
2170 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); in gfx_v6_0_cp_compute_resume()
2185 ring->wptr = 0; in gfx_v6_0_cp_compute_resume()
2189 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); in gfx_v6_0_cp_compute_resume()
2196 for (i = 0; i < 2; i++) { in gfx_v6_0_cp_compute_resume()
2202 return 0; in gfx_v6_0_cp_compute_resume()
2235 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v6_0_enable_gui_idle_interrupt()
2262 return 0; in gfx_v6_0_cp_resume()
2275 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v6_0_ring_emit_pipeline_sync()
2276 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); in gfx_v6_0_ring_emit_pipeline_sync()
2278 amdgpu_ring_write(ring, 0xffffffff); in gfx_v6_0_ring_emit_pipeline_sync()
2283 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v6_0_ring_emit_pipeline_sync()
2284 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_pipeline_sync()
2285 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v6_0_ring_emit_pipeline_sync()
2286 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_pipeline_sync()
2299 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ in gfx_v6_0_ring_emit_vm_flush()
2300 WAIT_REG_MEM_ENGINE(0))); /* me */ in gfx_v6_0_ring_emit_vm_flush()
2302 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_vm_flush()
2303 amdgpu_ring_write(ring, 0); /* ref */ in gfx_v6_0_ring_emit_vm_flush()
2304 amdgpu_ring_write(ring, 0); /* mask */ in gfx_v6_0_ring_emit_vm_flush()
2305 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v6_0_ring_emit_vm_flush()
2309 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in gfx_v6_0_ring_emit_vm_flush()
2310 amdgpu_ring_write(ring, 0x0); in gfx_v6_0_ring_emit_vm_flush()
2313 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v6_0_ring_emit_vm_flush()
2314 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_vm_flush()
2315 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v6_0_ring_emit_vm_flush()
2316 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_vm_flush()
2327 WRITE_DATA_DST_SEL(0))); in gfx_v6_0_ring_emit_wreg()
2329 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_wreg()
2378 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); in gfx_v6_0_rlc_init()
2386 return 0; in gfx_v6_0_rlc_init()
2391 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); in gfx_v6_0_enable_lbpw()
2394 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v6_0_enable_lbpw()
2395 WREG32(mmSPI_LB_CU_MASK, 0x00ff); in gfx_v6_0_enable_lbpw()
2403 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v6_0_wait_for_rlc_serdes()
2404 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0) in gfx_v6_0_wait_for_rlc_serdes()
2409 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v6_0_wait_for_rlc_serdes()
2410 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0) in gfx_v6_0_wait_for_rlc_serdes()
2443 WREG32(mmRLC_CNTL, 0); in gfx_v6_0_rlc_stop()
2462 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v6_0_rlc_reset()
2472 if ((tmp & 0xF0000000) == 0xB0000000) in gfx_v6_0_lbpw_supported()
2497 WREG32(mmRLC_RL_BASE, 0); in gfx_v6_0_rlc_resume()
2498 WREG32(mmRLC_RL_SIZE, 0); in gfx_v6_0_rlc_resume()
2499 WREG32(mmRLC_LB_CNTL, 0); in gfx_v6_0_rlc_resume()
2500 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff); in gfx_v6_0_rlc_resume()
2501 WREG32(mmRLC_LB_CNTR_INIT, 0); in gfx_v6_0_rlc_resume()
2502 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); in gfx_v6_0_rlc_resume()
2504 WREG32(mmRLC_MC_CNTL, 0); in gfx_v6_0_rlc_resume()
2505 WREG32(mmRLC_UCODE_CNTL, 0); in gfx_v6_0_rlc_resume()
2514 for (i = 0; i < fw_size; i++) { in gfx_v6_0_rlc_resume()
2518 WREG32(mmRLC_UCODE_ADDR, 0); in gfx_v6_0_rlc_resume()
2523 return 0; in gfx_v6_0_rlc_resume()
2535 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080); in gfx_v6_0_enable_cgcg()
2539 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in gfx_v6_0_enable_cgcg()
2540 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in gfx_v6_0_enable_cgcg()
2541 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff); in gfx_v6_0_enable_cgcg()
2546 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff); in gfx_v6_0_enable_cgcg()
2568 u32 data, orig, tmp = 0; in gfx_v6_0_enable_mgcg()
2572 data = 0x96940200; in gfx_v6_0_enable_mgcg()
2584 data &= 0xffffffc0; in gfx_v6_0_enable_mgcg()
2590 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in gfx_v6_0_enable_mgcg()
2591 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in gfx_v6_0_enable_mgcg()
2592 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff); in gfx_v6_0_enable_mgcg()
2597 data |= 0x00000003; in gfx_v6_0_enable_mgcg()
2613 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in gfx_v6_0_enable_mgcg()
2614 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in gfx_v6_0_enable_mgcg()
2615 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff); in gfx_v6_0_enable_mgcg()
2652 data &= ~0x8000; in gfx_v6_0_enable_cp_pg()
2654 data |= 0x8000; in gfx_v6_0_enable_cp_pg()
2668 u32 bo_offset = 0;
2678 for (me = 0; me < max_me; me++) {
2679 if (me == 0) {
2721 for (i = 0; i < table_size; i ++) {
2734 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10)); in gfx_v6_0_enable_gfx_cgpg()
2738 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); in gfx_v6_0_enable_gfx_cgpg()
2793 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); in gfx_v6_0_init_gfx_cgpg()
2807 u32 count = 0; in gfx_v6_0_get_csb_size()
2812 return 0; in gfx_v6_0_get_csb_size()
2824 return 0; in gfx_v6_0_get_csb_size()
2840 u32 count = 0, i; in gfx_v6_0_get_csb_buffer()
2849 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v6_0_get_csb_buffer()
2852 buffer[count++] = cpu_to_le32(0x80000000); in gfx_v6_0_get_csb_buffer()
2853 buffer[count++] = cpu_to_le32(0x80000000); in gfx_v6_0_get_csb_buffer()
2860 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000); in gfx_v6_0_get_csb_buffer()
2861 for (i = 0; i < ext->reg_count; i++) in gfx_v6_0_get_csb_buffer()
2871 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); in gfx_v6_0_get_csb_buffer()
2873 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v6_0_get_csb_buffer()
2876 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v6_0_get_csb_buffer()
2877 buffer[count++] = cpu_to_le32(0); in gfx_v6_0_get_csb_buffer()
2941 amdgpu_ring_write(ring, 0x80000000); in gfx_v6_ring_emit_cntxcntl()
2942 amdgpu_ring_write(ring, 0); in gfx_v6_ring_emit_cntxcntl()
2973 /* type 0 wave data */ in gfx_v6_0_read_wave_data()
2974 dst[(*no_fields)++] = 0; in gfx_v6_0_read_wave_data()
3001 adev, simd, wave, 0, in gfx_v6_0_read_wave_sgprs()
3040 return 0; in gfx_v6_0_early_init()
3073 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v6_0_sw_init()
3085 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v6_0_sw_init()
3095 ring->doorbell_index = 0; in gfx_v6_0_sw_init()
3116 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v6_0_sw_fini()
3118 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v6_0_sw_fini()
3123 return 0; in gfx_v6_0_sw_fini()
3141 adev->gfx.ce_ram_size = 0x8000; in gfx_v6_0_hw_init()
3154 return 0; in gfx_v6_0_hw_fini()
3186 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v6_0_wait_for_idle()
3188 return 0; in gfx_v6_0_wait_for_idle()
3196 return 0; in gfx_v6_0_soft_reset()
3227 if (ring == 0) { in gfx_v6_0_set_compute_eop_interrupt_state()
3240 if (ring == 0) { in gfx_v6_0_set_compute_eop_interrupt_state()
3282 return 0; in gfx_v6_0_set_priv_reg_fault_state()
3307 return 0; in gfx_v6_0_set_priv_inst_fault_state()
3320 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state); in gfx_v6_0_set_eop_interrupt_state()
3328 return 0; in gfx_v6_0_set_eop_interrupt_state()
3336 case 0: in gfx_v6_0_eop_irq()
3337 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v6_0_eop_irq()
3346 return 0; in gfx_v6_0_eop_irq()
3355 case 0: in gfx_v6_0_fault()
3356 ring = &adev->gfx.gfx_ring[0]; in gfx_v6_0_fault()
3374 return 0; in gfx_v6_0_priv_reg_irq()
3383 return 0; in gfx_v6_0_priv_inst_irq()
3405 return 0; in gfx_v6_0_set_clockgating_state()
3430 return 0; in gfx_v6_0_set_powergating_state()
3440 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ in gfx_v6_0_emit_mem_sync()
3441 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ in gfx_v6_0_emit_mem_sync()
3442 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ in gfx_v6_0_emit_mem_sync()
3464 .align_mask = 0xff,
3465 .nop = 0x80000000,
3492 .align_mask = 0xff,
3493 .nop = 0x80000000,
3519 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v6_0_set_ring_funcs()
3521 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v6_0_set_ring_funcs()
3554 int i, j, k, counter, active_cu_number = 0; in gfx_v6_0_get_cu_info()
3555 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; in gfx_v6_0_get_cu_info()
3565 memset(cu_info, 0, sizeof(*cu_info)); in gfx_v6_0_get_cu_info()
3570 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v6_0_get_cu_info()
3571 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_get_cu_info()
3573 ao_bitmap = 0; in gfx_v6_0_get_cu_info()
3574 counter = 0; in gfx_v6_0_get_cu_info()
3575 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v6_0_get_cu_info()
3580 cu_info->bitmap[0][i][j] = bitmap; in gfx_v6_0_get_cu_info()
3582 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v6_0_get_cu_info()
3597 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v6_0_get_cu_info()
3608 .minor = 0,
3609 .rev = 0,